Method for forming a polysilicon layer in a polycide process flow
AssigneeVanguard International Semiconductor Corporation
InventorsChih-Cherng Liao, Jiunn-Liang Yu, Chan-Jen Kuo, Chi-San Wu, Yun-Chi Jiang
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Abstract
A method for preventing void formation in a gate of a transistor formed in a substrate is disclosed. The method comprises: forming a gate oxide layer on the substrate; forming a polysilicon layer on the gate oxide layer; performing an ion implantation on the polysilicon layer, the ion implantation performed with a power approximately 30 KeV and a dosage about more than 1015 atoms/cm2; and forming a silicide layer on the polysilicon layer.
Claims14
A method for preventing void formation in a gate of a transistor formed in a substrate, the method comprising:
- forming a gate oxide layer on said substrate;
- forming a polysilicon layer on said gate oxide layer;
- performing an ion implantation on said polysilicon layer, said ion implantation performed with a power approximately 30 KeV and a dosage about 1015 atoms/cm2;
- and
- forming a silicide layer on said polysilicon layer.
A method for forming a transistor on a substrate, said method comprising:
- forming a gate oxide layer on said substrate;
- forming a polysilicon layer on said gate oxide layer;
- performing a first ion implantation with a power of about more than 30 KeV on said polysilicon layer;
- forming a silicide layer on said polysilicon layer;
- patterning and etching said polysilicon layer and said silicide layer to form a gate structure;
- annealing said polysilicon layer and said silicide layer;
- performing a second ion implantation to form a first doped region in said substrate;
- forming a spacer on the side wall of said gate structure to form a gate electrode;
- performing a third ion implantation to form a second doped region in said substrate;
- forming a dielectric layer over said gate electrode and said first and second doped region;
- patterning said dielectric layer to expose said second doped region;
- forming a conductive layer over said dielectric layer and said second doped region;
- patterning and etching said conductive layer to be coupled to said second doped region;
- and
- forming a passivation layer on said conductive layer and said dielectric layer.
A method for preventing void formation in a gate of a transistor formed in a substrate, the method comprising:
- forming a gate oxide layer on said substrate;
- forming a polysilicon layer on said gate oxide layer;
- and
- performing an ion implantation on said polysilicon layer, said ion implantation performed with a power of at least 30 KeV.
Dependencies are inferred from the claim text.