US 6,191,018 B1 · Method for selective resistivity adjustment of polycide lines for enhanced design flexibility and improved space utilization in sub-micron integrated circuits

Abstract

A method for forming a polycide layer wherein the silicide layer is blanket deposited over a polysilicon layer and selectively ion implanted through a mask to form regions of a higher resistivity than the masked regions. The implanted polycide layer is then annealed by RTA and patterned to form the conductors, gate electrodes and interconnects from the low resistivity regions and resistive components of an integrated circuit from the high resistivity regions. The capability of selecting from high and low resistive regions in a single polycide layer permits the design of resistive components with smaller areas than would be permitted if the resistive components were formed of a single low resistivity layer. This extra degree of freedom permits the designer to optimize device density and device performance without compromising either. The procedure utilizes a additional masking step utilizing a block-out mask.

Claims12

Dependent claims

A method of forming a polycide layer having a region of a first resistivity and a region of a second resistivity comprising:

(a) providing a silicon wafer;
(b) forming an insulative layer over said silicon wafer;
(c) forming a polysilicon layer of said first resistivity over said insulative layer;
(d) forming a refractory metal silicide layer on said polysilicon layer;
(e) forming a mask on said silicide layer exposing a portion of said suicide layer;
(f) implanting ions into said portion, thereby forming a region of said second resistivity;
(g) removing said mask;
(h) subjecting said substrate wafer to a rapid thermal anneal;
and
(i) patterning said polycide layer to form a first plurality of islands of said first resistivity and a second plurality of islands of said second resistivity wherein said first resistivity is higher than said second resistivity and said first plurality of islands are patterned to form resistive elements and said second plurality are patterned to form interconnective elements.

7 more elements

Dependencies are inferred from the claim text.

Method for selective resistivity adjustment of polycide lines for enhanced design flexibility and improved space utilization in sub-micron integrated circuits

Life of this patent

Method for selective resistivity adjustment of polycide lines for enhanced design flexibility and improved space utilization in sub-micron integrated circuits

Life of this patent

Abstract

Claims12