Method for fabricating high-voltage device

A method for forming a high-voltage MOS device, comprising:

• providing a silicon substrate;
• forming a gate oxide layer above said silicon substrate;
• depositing a polysilicon layer over said gate oxide layer;
• forming a photoresist layer over said polysilicon layer and gate oxide layer, wherein said photoresist layer is defined and etched to form a gate;
• removing the photoresist layer;
• depositing and etching a dielectric layer above said polysilicon layer by using high-density plasma CVD to result in the inherit triangle shape of high-density plasma CVD film characteristic;
• implanting N-type ions into the silicon substrate to form N-type grad therein;
• implanting N+-type ions into said grad to form source/drain regions.

A method for forming a high-voltage MOS device, comprising:

• providing a silicon substrate;
• forming a gate oxide layer above said silicon substrate;
• depositing a polysilicon layer over said gate oxide layer;
• forming a photoresist layer over said polysilicon layer and gate oxide layer, wherein said photoresist layer is defined and etched to form a gate;
• removing the photoresist layer;
• depositing and etching a dielectric layer above said polysilicon layer by using high density plasma CVD to result in the inherit triangle shape of high-density plasma CVD film characteristic;
• implanting first ions into the substrate to form a grad therein by using said high-density plasma dielectric layer as a mask;
• implanting second ions into said grad to form source/drain regions by using said high-density plasma dielectric layer as a mask, wherein said second ions having dosage greater than said first ions.