Method of fabricating a MOS transistor on a semiconductor wafer
AssigneeUnited Microelectronics Corp.
InventorsHua-Chou Tseng, Chien-Ting Lin
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Abstract
The present invention relates to a method of fabricating a MOS transistor on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate. A gate is first formed in a predetermined area on the surface of the semiconductor wafer. A first ion implantation process is then performed to form a doped area on the surface of the silicon substrate adjacent to the gate, the doped area serving as a heavily doped drain (HDD). A uniform and oxygen-free dielectric layer is formed on the surface of the semiconductor wafer that covers the gate. A spacer is formed on each wall of the gate. Finally, a second ion implantation process is performed to form a source and a drain on the surface of the silicon substrate adjacent to the spacer.
Claims14
A method of fabricating a metal-oxide-semiconductor (MOS) transistor on a semiconductor wafer, the semiconductor wafer comprising a silicon substrate, the method comprising:
- forming a gate in a predetermined area on the surface of the semiconductor wafer;
- performing a first ion implantation process to form a doped area on the surface of the silicon substrate adjacent to the gate, the doped area serving as a heavily doped drain (HDD);
- forming a uniform and oxygen-free dielectric layer on the surface of the semiconductor wafer that covers the gate;
- forming a silicon oxide layer on the surface of the dielectric layer;
- performing an anisotropic dry etching process to vertically remove a portion of the silicon oxide layer, a remaining portion of the silicon oxide layer forming a spacer on each wall of the gate;
- and
- performing a second ion implantation process to form a source and a drain on the surface of the silicon substrate adjacent to the spacer.
A method of fabricating a PMOS transistor on the surface of a silicon substrate of a semiconductor wafer, the silicon substrate comprising an N-well, the method comprising:
- forming a gate in a predetermined area on the surface of the N-well;
- performing a boron (B) ion implantation process to form a doped area on the surface of the silicon substrate adjacent to the gate, the doped area serving as a heavily doped drain (HDD);
- forming a uniform silicon nitride layer with a thickness of 40 to 100 angstroms on the surface of the semiconductor wafer that covers the gate;
- forming a silicon oxide layer on the surface of the silicon nitride layer;
- performing an anisotropic dry etching process to vertically remove a portion of the silicon oxide layer, a remaining portion of the silicon oxide layer forming a spacer on each wall of the gate;
- and
- performing an ion implantation process to form a source and a drain on the surface of the silicon substrate adjacent to the spacer.
Dependencies are inferred from the claim text.