US 6,190,971 B1 · Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region

Abstract

A method and structure for manufacturing an integrated circuit device includes forming a storage device in a substrate, lithographically forming a gate opening in the substrate over the storage device, forming first spacers in the gate opening, forming a strap opening in the substrate using the first spacers to align the strap opening, forming second spacers in the strap opening, forming an isolation opening in the substrate using the second spacers to align the isolation opening, filling the isolation opening with an isolation material, removing the first spacers and a portion of the second spacers to form a step in the gate opening, (wherein the second spacers comprise at least one conductive strap electrically connected to the storage device) forming a first diffusion region in the substrate adjacent the conductive strap, forming a gate insulator layer over the substrate and the step, forming a gate conductor over a portion of the gate insulator layer above the step, forming a second diffusion region in the substrate adjacent the gate conductor and forming a contact over the diffusion region and isolated from the gate conductor, wherein a voltage in the gate conductor forms a conductive region in the substrate adjacent the step and the conductive region electrically connects the strap and the contact.

Claims14

Dependent claims

A method of manufacturing an integrated circuit chip comprising:

forming an opening having at least one step in a substrate;
forming a first conductor in said opening below said step;
forming a first diffusion region in said substrate adjacent said first conductor and below said step;
forming a gate conductor over said step and in said opening;
forming a second conductor over said substrate adjacent said gate conductor;
and
forming a second diffusion region in said substrate adjacent said second conductor.

4 more elements

A method of manufacturing an integrated circuit device comprising:

forming a storage device in a substrate;
lithographically forming a gate opening in said substrate over said storage device;
forming first spacers in said gate opening;
forming a strap opening in said substrate using said first spacers to align said strap opening;
forming second spacers in said strap opening;
forming an isolation opening in said substrate using said second spacers to align said isolation opening;
filling said isolation opening with an isolation material;
removing said first spacers and a portion of said second spacers to form a step in said gate opening, wherein said second spacers comprise at least one conductive strap electrically connected to said storage device;
forming a first diffusion region in said substrate adjacent said conductive strap;
forming a gate insulator layer over said substrate and said step;
forming a gate conductor over a portion of said gate insulator layer above said step;
forming a second diffusion region in said substrate adjacent said gate conductor;
and
forming a contact over said second diffusion region and isolated from said gate conductor,
wherein a voltage in said gate conductor forms a conductive region in said substrate adjacent said step, said conductive region electrically connecting said strap and said contact.

12 more elements

Dependencies are inferred from the claim text.

Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region

Life of this patent

Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region

Life of this patent

Abstract

Claims14