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US 6,190,954 B1Granted
Robust latchup-immune CMOS structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJian-Hsing Lee, Shui-Hung Chen, Jiaw Ren Shih
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Abstract
A method is disclosed to provide for more robust latchup-immune CMOS transistors by increasing the breakover voltage VBO, or trigger point, of the parasitic npn and pnp transistors present in CMOS structures. These goals have been achieved by adding a barrier layer to both the n-well and p-well of a twin-well CMOS structure, thus increasing the energy gap for electrons and holes of the parasitic npn and pnp transistor, respectively.
Claims10
A method of providing a robust latchup-immune MOSFET structure, comprising the steps of:
- providing a p-type silicon substrate;
- providing a p-well in said p-type substrate;
- providing an n-well in said p-type substrate;
- depositing a p-well barrier in said p-well, said p-well barrier having a thickness ranging from 50 to 250 nm;
- depositing an n-well barrier in said n-well, said n-well barrier having a thickness ranging from 50 to 250 nm;
- creating a p-channel MOSFET transistor in said n-well;
- creating an n-channel MOSFET transistor in said p-well;
- providing said p-channel transistor with a connection to a voltage supply;
- and
- providing said n-channel transistor with a connection to a reference potential.
7 more elements
Dependencies are inferred from the claim text.