US 6,189,136 B1 · Design level optical proximity correction methods

Abstract

A method for integrating correction features onto selected design features of an integrated circuit mask. The method includes identifying a minimum dimension in the integrated circuit mask. The minimum dimension is configured to define transistor gate electrode features or any critical feature geometry. The method then includes removing feature geometries that are dimensionally larger than the minimum dimension. After the removing operation, correction features are integrated with selected ends of the transistor electrode features that have the minimum dimension to produce corrected transistor gate electrode features. Then, the method includes the operation of adding the corrected transistor gate electrode features to the removed feature geometries that are dimensionally larger than the minimum dimension to produce a corrected integrated circuit mask.

Claims20

Dependent claims

A method for correcting features of an integrated circuit design that is embodied on a mask and is in the form of a digital file, comprising:

providing a transistor gate feature mask having transistor gates that have minimum gate lengths and contact heads;
sizing down the transistor gates by about half of the minimum gate lengths, such that only reduced size contact heads remain;
sizing up the reduced size contact heads to produce individual contact heads;
inverting the individual contact heads;
performing a logical AND operation between the transistor gate feature mask and the inverted individual contact heads to produce modified transistor gates without the contact heads;
adding correction features to selected ends of the modified transistor gates without contact heads to produce corrected transistor gates;
and
performing a logical OR operation between the corrected transistor gates and the transistor gate feature mask.

5 more elements

A method for integrating correction features onto selected design features of an integrated circuit mask, comprising:

identifying a minimum dimension in the integrated circuit mask, the minimum dimension defining transistor gate electrode features;
removing feature geometries that are dimensionally larger than the minimum dimension;
integrating the correction features to selected ends of the transistor electrode features that have the minimum dimension to produce corrected transistor gate electrode features;
and
adding the corrected transistor gate electrode features to the removed feature geometries that are dimensionally larger than the minimum dimension to produce a corrected integrated circuit mask.

2 more elements

Dependencies are inferred from the claim text.

Design level optical proximity correction methods

Life of this patent

Design level optical proximity correction methods

Life of this patent

Abstract

Claims20