Structure of a channel write/erase flash memory cell and manufacturing method and operating method thereof
OwnerChing-Hsiang Hsu, Ching-Song Yanginventors
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Abstract
A channel write/erase flash memory cell structure together with its method of manufacture and mode of operation. The flash memory cell structure is formed by implanting P-type ions into a substrate to form a shallow-doped region, and then implanting N-type ions to form the drain terminal of the flash memory cell. Next, a deep-doped region that acts as a P-well is formed underneath the drain terminal. Method of manufacturing the channel write/erase memory cell and its mode of operation is also discussed.
Claims4
A method of operating a channel write/erase flash memory cell by applying a word line voltage, a source terminal voltage and a bit line voltage to the controlling gate, the source terminal and the drain terminal of the flash memory cell respectively, wherein the drain terminal and the P-type well of the flash memory cell are short-circuited together, the method including:
- applying a high voltage to the word line, applying a voltage lower than the word line voltage to the source terminal and maintaining the bit line voltage at a floating state in the execution of a memory erase operation;
- applying a low voltage to the word line, applying a voltage higher than the word line to the bit line and maintaining the source terminal voltage at a floating state in carrying out a programming operation;
- and
- applying a moderate voltage to the word line, applying a voltage lower than the word line to the source terminal and applying a voltage lower than the source voltage to the bit line in carrying out a memory read operation.
Dependencies are inferred from the claim text.