Frequency adjustments by patterning micro-strips to form serially connected capacitors or inductor-capacitor (LC) Circuit

A method for making an electronic device by interconnecting a plurality of circuit elements comprising steps of:

• patterning a first conductive layer to form micro-strips for interconnecting said plurality of circuit elements;
• forming a new inductor by cutting partially one of said micro-strips connected between two capacitors for forming a serially coupled inductance-capacitance (LC) circuit on said first patterned conductive layer;
• interconnecting a resistor to a transistor by one of said micro-strips of said first patterned conductive layer;
• placing a first insulation layer underneath said first patterned conductive layer and placing a second patterned conductive layer underneath said first insulation layer and connecting said second patterned conductive layer to a ground voltage;
• placing a second insulation layer underneath said second patterned conductive layer and placing a third patterned conductive layer underneath said second insulation layer;
• and
• opening through holes in said first and said second insulation layer and interconnecting said circuit elements disposed on said first patterned conductive layer to said third patterned conductive layer with an interlayer conductor passing through said through holes.

An electronic device formed by interconnecting a plurality of circuit elements comprising:

• a first patterned conductive layer constituting micro-strips for interconnecting said plurality of circuit elements;
• one of said micro-strips constituting an open-transmission line having a first end connected to a first capacitor and a second end as an open-end, wherein said open transmission line is cut into separate segments with said separate segments constituting a new capacitor in series connection with said first capacitor for providing a reduced combined capacitance on said first patterned conductive layer;
• a resistor and a transistor interconnected by said micro-strips of said patterned conductive layer;
• a second patterned conductive layer insulated from said first patterned conductive layer by a first insulation layer;
• a third patterned conductive layer for providing a ground voltage disposed between and insulated from said first conductive and second conductive layers by a first and a second insulation layer;
• and
• said first and a second insulation layers includes through holes filled with conductive filling material for interconnecting said circuit elements disposed on said first patterned conductive layer, and said second patterned conductive layer.

An electronic device formed by interconnecting a plurality of circuit elements comprising:

• a first patterned conductive layer constituting micro-strips for interconnecting said plurality of circuit elements;
• one of said micro-strips connected between two capacitors is cut partially for providing a serially coupled inductance-capacitance (LC) circuit on said first patterned conductive layer;
• a resistor and a transistor interconnected by one of said micro-strips of said first patterned conductive layer;
• a second patterned conductive layer insulated from said first patterned conductive layer by a first insulation layer;
• said first insulation layer includes through holes filled with conductive filling material for interconnecting said circuit elements disposed on said first patterned conductive layer and said second patterned conductive layer;
• a third patterned conductive layer for providing a ground voltage disposed between and insulated from said first conductive and second conductive layers by said first insulation layer and a second insulation layer;
• and
• said first and second insulation layers include through holes filled with conductive filing material for interconnecting said circuit elements disposed on said first patterned conductive layer and said second conductive layer.

An electronic device formed by interconnecting a plurality of circuit elements comprising:

• a plurality of patterned conductive layers constituting micro-strips for interconnecting said plurality of circuit elements disposed on each of said patterned conductive layers;
• and
• one of said micro-sips constituting an open-transmission line having a first end connected to a first capacitor and a second end as an open-end cut into separate segments with said separate segments constituting a new capacitor in series connection with said first capacitor for providing a reduced combined capacitance;
• a plurality of insulation layer disposed between said patterned conductive layers;
• and
• each of said insulation layers includes through holes filled with conductive filling material for interconnecting said circuit elements disposed on said plurality of patterned conductive layers.