Normally conducting dual thyristor
AssigneeCentre National De La Recherche Scientifique
InventorsJean-Louis Sanchez, Jean Jalade, Jean-Pierre Laur, Henri Foch
Life of this patent
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Abstract
The present invention relates to a component forming a normally on dual thyristor, which can be turned off by a voltage pulse on the control electrode, including a thyristor, a first depletion MOS transistor, the gate of which is connected to the source, connected between the anode gate and the cathode of the thyristor, and a second enhancement MOS transistor, the gate of which is connected to a control terminal.
Claims8
A component forming a dual thyristor, which is normally on and which can be turned off by a voltage pulse on a control electrode, including:
- a thyristor (Th) having a cathode (K), an anode, a cathode gate (GK) and an anode gate (GA),
- resistive means formed of a first depletion MOS transistor (MD1) having a drain, a source, a gate and a substrate, the gate being connected to the source, the substrate being connected to the cathode gate terminal, said first transistor being connected between the anode gate (GA) and the cathode (K), and
- a controlled switching means formed of a second enhancement MOS transistor (ME2) having a drain, a source, a gate and a substrate, the gate being connected to a control terminal (G) and the substrate being connected to the cathode gate (GK) terminal, said second transistor being connected between the cathode gate (GK) and the cathode (K), and,
- maintaining means for maintaining conduction between the cathode gate and cathode in response to said switching means comprising:
- a third enhancement MOS transistor (ME3) having a gate, a source, a drain and a substrate, the substrate of which is connected to the cathode gate terminal (GK), in parallel with the second transistor (ME2);
- a zener diode (Z) connected between the cathode of the thyristor and a node (C) connected to the gate of the third transistor (ME3);
- and
- a fourth depletion MOS transistor (MD4) having a gate, a source, a drain and a substrate and connected between said node (C) and the anode gate of the thyristor, the gate of the fourth transistor being connected to the cathode (K) and its substrate being connected to said node (C).
Dependencies are inferred from the claim text.