Rough electrode (high surface area) from Ti and TiN
AssigneeMicron Technology, Inc.
InventorsGaro J. Derderian, Gurtej S. Sandhu
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Abstract
A technique for forming high surface area electrode or storage nodes for a capacitor and devices formed thereby, including depositing a first layer of conductive material on a substrate, such that a discontinuous layer is formed. A second conductive material layer is deposited over the discontinuous first conductive material layer, such that the second conductive material layer grows or accumulates on the discontinuous first conductive material layer at a faster rate than on the exposed areas of the substrate in the discontinuous first conductive material layer to form a rough conductive material layer.
Claims39
A storage node structure for a semiconductor capacitor having a discontinuous first conductive material layer including at least one exposed area exposing a portion of a substrate and a second conductive material layer over said discontinuous first conductive material layer and said at least one exposed area, a thickness of said second conductive material layer over said discontinuous first conductive material layer being greater than a thickness of said second conductive material layer over said portion of said substrate within said at least one exposed area, formed by a method comprising:
- providing said substrate;
- depositing said discontinuous first conductive material layer on said substrate, wherein said discontinuous first conductive material layer defines at least one exposed area exposing said portion of said substrate within said discontinuous first conductive material layer;
- and
- depositing said second conductive material layer over said discontinuous first conductive material layer and said at least one exposed area, said second conductive material layer forming on said discontinuous first conductive material layer at a faster rate than on said portion of said substrate within said at least one exposed area.
A semiconductor device having a capacitor including a discontinuous first conductive material layer including at least one exposed area exposing a portion of a substrate and a second conductive material layer over said discontinuous first conductive material layer and said at least one exposed area, a thickness of said second conductive material layer over said discontinuous first conductive material layer being greater than a thickness of said second conductive material layer over said portion of said substrate within said at least one exposed area, formed by a method comprising:
- providing said substrate;
- depositing said discontinuous first conductive material layer on said substrate, wherein said discontinuous first conductive material layer defines at least one exposed area exposing said portion of said substrate within said discontinuous first conductive material layer;
- and
- depositing said second conductive material layer over said discontinuous first conductive material layer and said at least one exposed area, said second conductive material layer growing or accumulating on said discontinuous first conductive material layer at a faster rate than on said portion of said substrate within said at least one exposed area.
A capacitor storage node, comprising:
- a discontinuous first conductive material layer on a substrate, wherein said discontinuous first conductive material layer defines at least one exposed area exposing said substrate within said discontinuous first conductive material layer;
- and
- a second conductive material layer over said discontinuous first conductive material layer and said at least one exposed area, wherein said second conductive material layer has a thickness over said discontinuous first conductive material layer greater than a thickness over said at least one exposed area defined within said discontinuous first conductive material layer.
A memory cell having at least one capacitor storage node, comprising:
- a discontinuous first conductive material layer on a substrate, wherein said discontinuous first conductive material layer defines at least one open area exposing said substrate within said discontinuous first conductive material layer;
- and
- a second conductive material layer over said discontinuous first conductive material layer and said at least one open area, wherein said second conductive material layer has a thickness over said discontinuous first conductive material layer greater than a thickness over said at least one open area defined within said discontinuous first conductive material layer.
A random access memory chip having at least one memory cell having at least one capacitor storage node, comprising:
- a discontinuous first conductive material layer on a substrate, wherein said discontinuous first conductive material layer defines at least one open area exposing said substrate within said discontinuous first conductive material layer;
- and
- a second conductive material layer over said discontinuous first conductive material layer and said at least one open area, wherein said second conductive material layer has a thickness over said discontinuous first conductive material layer greater than a thickness over said at least one open area defined within said discontinuous first conductive material layer.
Dependencies are inferred from the claim text.