Method for manufacturing memory cell with increased threshold voltage accuracy
AssigneeWinbond Electronic Corp.
InventorWen-Ying Wen
Life of this patent
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Abstract
A method is provided for manufacturing a memory cell with a increased threshold voltage accuracy. The memory cell has a substrate including a plurality of first conducting lines in a first direction and a plurality of second conducting lines in a second direction. The method includes the steps of forming a photoresist layer over the first and the second conducting lines, forming a window on the photoresist layer to expose a portion of the second conducting lines, thinning the portion of the second conducting lines in the windows, and doping impurities into the substrate between two of the first conducting lines to form the memory cell.
Claims21
A method for manufacturing a memory cell, with increased accuracy in a threshold voltage thereof, having a substrate, forming thereon a plurality of first conducting lines in a first direction, forming thereon a plurality of second conducting lines in a second direction, comprising steps of:
- forming a dielectric layer over said first and said second conducting lines;
- removing a portion of said dielectric layer to expose said second conducting lines;
- forming a photoresist layer over said first and said second conducting lines;
- forming a window on said photoresist layer to expose a portion of said second conducting lines;
- thinning said portion of said second conducting lines in said window;
- and
- doping impurities into said substrate between two of said first conducting lines for a threshold voltage adjustment to form said memory cell.
A method for manufacturing a memory cell, with increased accuracy in a threshold voltage thereof, having a substrate, formed thereon a plurality of first conducting lines in a first direction, forming thereon a plurality of second conducting lines in a second direction, comprising steps of:
- forming a dielectric layer over said first conducting lines and between any two of said second conducting lines;
- forming a photoresist layer over said first and said second conducting lines;
- forming a window on said photoresist layer to expose a portion of said second conducting lines;
- thinning said portion of said second conducting lines in said window;
- and
- doping impurities into said substrate between two of said first conducting lines for a threshold voltage adjustment to form said memory cell.
A method for manufacturing a memory cell having a substrate, forming thereon a plurality of first conducting lines in a first direction, forming thereon a plurality of second conducting lines in a second direction, wherein said second conducting lines comprises a polysilicon layer, forming thereon a tungsten silicide (WSix) layer, comprising steps of:
- forming a dielectric layer over said first conducting lines and between any two of said second conducting lines;
- forming a photoresist layer over said first and said second conducting lines;
- forming a window on said photoresist layer to expose a portion of said second conducting lines;
- thinning said portion of said second conducting lines in said window by reactive ion etching, wherein said etching is stopped when an exposed portion of said WSix layer is etched out;
- and
- doping impurities into said substrate between two of said first conducting lines for a threshold voltage adjustment to form said memory cell.
A method for manufacturing a memory cell having a substrate, forming thereon a plurality of first conducting lines in a first direction, forming thereon a plurality of second conducting lines in a second direction, wherein said second conducting lines comprises a polysilicon layer, forming thereon a tungsten silicide (WSix) layer, comprising steps of:
- forming a dielectric layer over said first conducting lines and between any two of said second conducting lines;
- forming a photoresist layer over said first and said second conducting lines;
- forming a window on said photoresist layer to expose a portion of said second conducting lines;
- thinning said portion of said second conducting lines in said window by reactive ion etching, wherein said etching is stopped when a remained portion of said polysilicon layer has a thickness range from 500 Å to 1000 Å;
- and
- doping impurities into said substrate between two of said first conducting lines for a threshold voltage adjustment to form said memory cell.
Dependencies are inferred from the claim text.