Vertical bipolar SRAM cell, array and system, and a method for making the cell and the array

A method of fabricating an SRAM memory cell comprising:

• forming a substrate assembly having at least one semiconductor layer;
• forming a first semiconductor layer over said at least one semiconductor layer;
• forming a second semiconductor layer over said first semiconductor layer;
• removing a portion of said second semiconductor layer to expose a first portion of said first semiconductor layer, said second semiconductor layer comprising a second semiconductor region having a second well face and a third semiconductor region having a third well face;
• forming an isolation structure in said portion of said second semiconductor layer;
• forming contacts for a first source and a first drain of a first transistor in said second semiconductor region;
• forming contacts for a second source and a second drain of a second transistor in said third semiconductor region;
• forming an insulation layer for a first gate for said first transistor and a second gate for said second transistor;
• forming a first conductive layer for coupling said first drain to said second gate;
• and
• forming a second conductive layer for coupling said first gate to said second drain;
• wherein a first bipolar transistor is formed having a first collector corresponding to said first semiconductor layer, a first base corresponding to said second semiconductor region, and a first emitter corresponding to said first drain contact;
• and wherein a second bipolar transistor is formed having a second collector corresponding to said first semiconductor layer, a second base corresponding to said third semiconductor region, and a second emitter corresponding to said second drain contact.