SRAM cell having bit line shorter than word line
AssigneeSamsung Electronics Co., Ltd.
InventorsHan-soo Kim, Kyeong-tae Kim
Life of this patent
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Abstract
An SRAM cell having a word line shorter than a bit line is provided. First and second driver transistors having first and second gate electrodes parallel to each other are formed on a semiconductor substrate, and a third gate electrode shared by first and second transfer transistors is formed between the first and the second gate electrodes. A word line electrically connected to the third electrode is perpendicular to the first and the second gate electrodes, and a pair of bit lines electrically connected to drain areas of the first and the second transfer transistors are perpendicular to the word line. Also, a pair of ground lines are electrically connected to the source areas of the first and the second driver transistors, and are parallel to the bit lines.
Claims26
An SRAM cell comprising:
- a semiconductor substrate;
- first and second driver transistors, having first and second gate electrodes arranged parallel to each other, formed on a top surface of the semiconductor substrate;
- first and second transfer transistors sharing a third gate electrode arranged between the first gate electrode and the second gate electrode, wherein the first and second transfer transistors are connected in series with the first and second driver transistors, respectively;
- and
- a word line electrically connected to the third gate electrode and crossing over the first and the second gate electrodes.
An SRAM cell comprising:
- a semiconductor substrate;
- first and second driver transistors, having first and second gate electrodes arranged parallel to each other on a top surface of the semiconductor substrate;
- first and second transfer transistors sharing a third gate electrode arranged between the first gate electrode and the second gate electrode, wherein the first and second transfer transistors are connected in series with the first and the second driver transistors, respectively;
- a pair of power lines passing over a source area of the first driver transistor and a source area of the second driver transistor, respectively, wherein the pair of power lines are arranged parallel to the first and second gate electrodes;
- a pair of load devices each connected to one end of each of the power lines, wherein the pair of load devices are passing over channel areas of the first and the second transfer transistors to extend to upper portions of the first and second gate electrodes, respectively;
- a first local interconnection line connecting together a first node junction shared by the first driver transistor and the first transfer transistor, the second gate electrode, and one end of the one of the load devices extending to an upper portion of the second gate electrode;
- a second local interconnection line connecting together a second node junction shared by the second driver transistor and the second transfer transistor, the first gate electrode, and one end of the other of the load devices extending to an upper portion of the first gate electrode;
- and
- a word line arranged perpendicular to the first and the second gate electrodes and passing between the first transfer transistor and the second transfer transistor, wherein the word line is electrically connected to the third gate electrode.
Dependencies are inferred from the claim text.