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US 6,184,557 B2Granted
I/O circuit that utilizes a pair of well structures as resistors to delay an ESD event and as diodes for ESD protection
AssigneeNational Semiconductor Corporation
InventorsPavel Poplevine, Alexander Kalnitsky, Hengyang (James) Lin, Albert Bergemont
Life of this patent
Estimating the term…
Abstract
The n-channel and p-channel driver transistors of an I/O circuit are electrostatic discharge (ESD) protected by utilizing a pair of well structures that resistively delay an ESD event from reaching the driver transistors, and that form diodes that direct the ESD event to the supply rail or ground of the circuit.
Claims14
An input/output circuit formed in a semiconductor material of a first conductivity type, the circuit comprising:
- a first well of a second conductivity type formed in the semiconductor material;
- a second well of the first conductivity type formed in the first well, the second well having a dopant concentration;
- a pair of spaced-apart first contacts of the first conductivity type formed in the second well, the first contacts having a dopant concentration that is greater than the dopant concentration of the second well;
- a third well of the second conductivity type formed in the semiconductor material, the third well having a dopant concentration, and a bottom surface;
- a pair of spaced-apart second contacts of the second conductivity type formed in the third well, the second contacts having a dopant concentration that is greater than the dopant concentration of the third well;
- an I/O pad connected to a first contact of the first contacts in the second well, and a first contact of the second contacts in the third well;
- a first driver transistor connected to a second contact of the first contacts in the second well;
- a second driver transistor connected to a second contact of the second contacts in the third well;
- and
- an internal circuit connected to the second contact of the first contacts, and the second contact of the second contacts.
7 more elements
An input/output circuit formed in a semiconductor material of a. first conductivity type, the circuit comprising:
- a first well of a second conductivity type formed in the semiconductor material;
- a second well of the first conductivity type formed in the first well, the second well having a dopant concentration;
- a pair of spaced-apart first contacts of the first conductivity type formed in the second well, the first contacts having a dopant concentration that is greater than the dopant concentration of the second well;
- a third well of the second conductivity type formed in the semiconductor material, the third well having a dopant concentration, and a bottom surface;
- a pair of spaced-apart second contacts of the second conductivity type formed in the third well, the second contacts having a dopant concentration that is greater than the dopant concentration of the third well;
- a fourth well of a second conductivity type formed in the semiconductor material;
- a fifth well of the first conductivity type formed in the fourth well, the fifth well having a dopant concentration;
- an I/O pad connected to a first contact of the first contacts in the second well, and a first contact of the second contacts in the third well;
- a first driver transistor connected to a second contact of the first contacts in the second well;
- a second driver transistor connected to a second contact of the second contacts in the third well;
- and
- an internal circuit connected to the second contact of the first contacts, and the second contact of the second contacts.
9 more elements
A method for forming an input/output circuit in a semiconductor material of a first conductivity type, the method comprising the steps of:
- forming a first well of a second conductivity type in the semiconductor material;
- forming a second well of the first conductivity type in the first well, the second well having a dopant concentration;
- forming a pair of spaced-apart first contacts of the first conductivity type in the second well, the first contacts having a dopant concentration that is greater than the dopant concentration of the second well;
- forming a third well of the second conductivity type in the semiconductor material, the third well having a dopant concentration, and a bottom surface;
- forming a pair of spaced-apart second contacts of the second conductivity type in the third well, the second contacts having a dopant concentration that is greater than the dopant concentration of the third well;
- forming an I/O pad connected to a first contact of the first contacts in the second well, and a first contact of the second contacts in the third well;
- forming a first driver transistor connected to a second contact of the first contacts in the second well;
- forming a second driver transistor connected to a second contact of the second contacts in the third well;
- and
- forming an internal circuit connected to the second contact of the first contacts, and the second contact of the second contacts.
7 more elements
Dependencies are inferred from the claim text.