DRAM cell and array to store two-bit data having merged stack capacitor and trench capacitor

An integrated circuit memory to retain digital data, fabricated on a semiconductor substrate having a surface implanted with a material of a first conductivity type, comprising:

• a) a plurality of twin bit DRAM cells arranged in a plurality of rows and columns, whereby each twin bit DRAM cell comprises:
• a first pass transistor having a source connected to a first bit line voltage generator, a gate connected to a word line voltage generator, and a drain,
• a trench capacitor in close proximity of said first pass transistor formed within the semiconductor substrate, whereby said trench capacitor includes a top plate connected to said drain of said first pass transistor, a bottom plate connected to a first biasing voltage source, and a first capacitor dielectric separating said top and bottom plates,
• a second pass transistor having a source connected to a second bit line voltage generator, a gate connected to a word line voltage generator, and a drain,
• a stack capacitor formed above the semiconductor substrate, having a first plate connected to the drain of the second pass transistor, a second plate connected to a second biasing voltage source, and a second capacitor dielectric separating said first and second plates, and
• an insulating layer placed between said trench capacitor and said stack capacitor to electrically isolate the trench capacitor from the stack capacitor;
• b) a plurality of word lines, whereby each word line is located on each row of the twin bit DRAM cells and connected to the gates of the first and second pass transistors on each row of the twin bit DRAM cells;
• c) a plurality of bit lines, whereby a pair bit line is located at the boundary of each column of twin bit DRAM cells and whereby one bit line is connected to the source of the first pass transistor of each twin bit DRAM cell on each column of twin bit DRAM cells and the other bit line of the pair of bit lines is connected to the source of the second pass transistor of each twin bit DRAM cell on each column of twin bit DRAM cells;
• d) a plurality of word line control circuits whereby each word line control circuit is coupled to each word line to select all the twin bit DRAM cells of one row of twin bit DRAM cells;
• e) a plurality of bit line control circuits whereby each bit line control circuit is connected to one bit line to establish a necessary bit line voltage level during a writing and reading of said twin bit DRAM cells on a column of twin bit DRAM cells;
• f) a plurality of sense amplifiers, whereby each sense amplifier is connected to one bit line to sense a level of charge representing the two bits of digital data retained within said twin bit DRAM cell;
• and
• g) a peripheral control circuit to provide control signals for the plurality of word line control circuits, bit line control circuits, twin bit sense amplifiers, and coupling-gate control circuits.