US 6,184,546 B2Granted

High barrier gate and tri-step doped channel field-effect transistor

AssigneeNational Science Council

InventorsW. C. Liu, W. S. Lour, W. L. Chang

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Abstract

A high-barrier gate field-effect transistor with an n+-GaAs/p+-GaInP/n-GaAs heterojunctions has been fabricated. The channel contains tri-step doped GaAs layers with a different doping level and thickness in each layer. Due to the significant conduction band discontinuity ΔEC between GaInP/GaAs heterointerface in the gate region, the gate barrier is increased and electrons are effectively confined in the channel. Furthermore, the existence of a valance band discontinuity ΔEv at the GaInP/GaAs heterointerface may prevent holes generated by impact ionization from reaching the gate region. The tri-step doped channel is adopted to increase the output current and linear transconductance. Therefore the device of this invention provides a high gate-drain breakdown voltage, a low leakage current and a high transconductance. Based on these advantages, the proposed device shows the promise for high-power, large signal analog, and digital switching circuit applications.

Claims12

Dependent claims

A high-barrier gate and tri-step doped channel field-effect transistor comprising:

a GaAs substrate;
a first undoped GaAs layer formed on said GaAs substrate;
a p+ doped GaAs layer formed on said first undoped layer:
a second undoped GaAs layer formed on the p+ doped GaAs layer formed on the p+ doped GaAs;
a tri-step n doped GaAs channel layer formed on said second undoped GaAs layer;
a p+ doped GaInP layer formed on tri-step n-doped GaAs channel layer so that a conductance band discontinuity occurs between a heterointerface of the p+ doped GaInP layer and the n doped GaAs channel layer in a gate region and causes electrons to be substantially confined in the channel layer, and a valance band discontinuity occurs at the heterointerface of the p+ doped GaInP layer and the n doped GaAs channel layer and inhibits holes generated by impact ionization from reaching the gate region;
an n+ doped GaAs ohmic contact layer formed on said p+ doped GaInP layer;
a first metal layer formed on the n+ doped GaAs ohmic contact layer to serve as an gate electrode;
and
a pair of second metal layers, formed on the n+ doped GaAs ohmic contact, respectively serving as the drain and source electrodes of said field effect transistor.

7 more elements

Dependencies are inferred from the claim text.