US 6,184,152 B2 · Method for fabricating stacked capacitor for a dynamic random access memory

Abstract

A method is provided for fabricating an array of memory cells for a dynamic random access memory. Each memory cell has an associated capacitor. An array of memory cell transistors is formed and each memory cell transistor has a source, a drain and a gate. The source is coupled to a bit line, and the gate is coupled to a word line. A lower conductive layer is formed over the array of memory cell transistors. The lower conductive layer is electrically coupled to the source of the memory cell transistors. A temporary insulation layer is formed over the lower conductive layer. A portion of the temporary insulation layer and the lower conductive layer are removed to form an electrically separate capacitor bottom plate for each memory cell and an inter-capacitor isolation region. A lateral portion of the temporary insulation layer is removed to form a capacitor sidewall spacing region. A protective layer is formed to fill the inter-capacitor isolation region and the capacitor sidewall spacing region. The temporary insulation layer is removed to expose a portion of the lower conductive layer. A portion of the exposed portion of the lower conductive layer is removed to form a U-shaped capacitor bottom plate. The protective layer is removed and a capacitor dielectric is formed. An upper conductive layer is formed to function as a top plate of the capacitor.

Claims33

Dependent claims

A method for fabricating an array of memory cells for a dynamic random access memory, each memory cell having an associated capacitor, comprising the steps of:

forming an array of memory cell transistors, one for each memory cell, each having a source, a drain coupled to a bit line, and a gate coupled to a word line;
forming a lower conductive layer over the array of memory cell transistors, the lower conductive layer being electrically coupled to the source of the memory cell transistors;
forming a temporary insulation layer over the lower conductive layer;
removing a portion of the temporary insulation layer and the lower conductive layer to form an electrically separate capacitor bottom plate for each memory cell and an inter-capacitor isolation region;
removing a lateral portion of the temporary insulation layer to form a capacitor sidewall spacing region;
forming a protective layer, the protective layer filling the inter-capacitor isolation region and the capacitor sidewall spacing region;
removing the temporary insulation layer to expose a portion of the lower conductive layer;
removing a portion of the exposed portion of the lower conductive layer to form the bottom plate in a U-shape;
removing the protective layer;
forming a capacitor dielectric adjacent the lower conductive layer;
and
forming an upper conductive layer adjacent the capacitor dielectric so as to form a top plate of the capacitor associated with each memory cell.

9 more elements

A method for fabricating a memory cell for a dynamic random access memory, the memory cell having a capacitor, comprising the steps of:

forming a memory cell transistor area on a substrate, the memory cell transistor area having a source area, a gate area and a drain area;
forming a memory cell transistor in the memory cell transistor area, the memory cell transistor having a source in the source area, a gate in the gate area and a drain in the drain area;
forming a first conductive layer in the gate area to form a word line;
forming a first insulation layer over the formed memory cell transistor and first conductive layer;
removing a portion of the first insulation layer adjacent the memory cell transistor area to reach the drain area to form a bit-line opening;
forming a second conductive layer, the second conductive layer filling the bit-line opening to electrically connect the drain area and to form a bit line;
forming a second insulation layer over the second conductive layer;
removing a portion of the second insulation layer over the source area to form a capacitor opening reaching the source area of the memory cell transistor;
forming a third conductive layer, the third conductive layer filling the capacitor opening and electrically connecting the source of the memory cell transistor;
forming a third insulation layer adjacent the third conductive layer;
removing a portion of the third insulation layer and the third conductive layer to form an inter-capacitor isolation region reaching the second insulation layer;
removing a lateral portion of the third insulation layer to form a capacitor sidewall spacing region;
forming a protective layer, the protective layer filling the inter-capacitor isolation region and the capacitor sidewall spacing region;
removing the third insulation layer to expose a portion of the third conductive layer;
removing a portion of the third conductive layer to form a U-shaped capacitor bottom plate;
removing the protective layer;
forming a capacitor dielectric adjacent the third conductive layer;
and
forming a fourth conductive layer adjacent the capacitor dielectric so as to form a top plate of the capacitor associated with each memory cell.

16 more elements

A method for fabricating a memory cell for a dynamic random access memory, the memory cell having a capacitor, comprising:

forming a memory cell transistor area on a substrate, the memory cell transistor area the memory cell transistor having a source in the source area, a gate in the gate area and a drain in the drain area;
forming a memory cell transistor in the memory cell transistor area, the memory transistor having a source in the source area, a gate in the gate area and a drain in the drain area;
forming a first conductive layer in the gate area to form a word line;
forming a first insulation layer over the formed memory cell transistor and first conductive layer;
removing a portion of the first insulation layer adjacent the memory cell transistor area to reach the drain area to form a bit-line opening;
forming a second conductive layer, the second conductive layer filling the bit-line opening to electrically connect the drain area and to form a bit line;
forming a second insulation layer over the second conductive layer;
removing a portion of the second insulation layer over the source area to form a capacitor opening reaching the source area of the memory cell transistor;
forming a third conductive layer, the third conductive layer filling the capacitor opening and electrically connecting the source of the memory cell transistor;
forming a third insulation layer adjacent the third conductive layer;
removing a portion of the third insulation and the third conductive layer to form an inter-capacitor isolation region reaching the second insulation layer;
removing a lateral portion of the third insulation layer to form a capacitor sidewall spacing region;
forming a protective layer, the protective layer filling the inter-capacitor isolation region and the capacitor sidewall spacing region;
removing the third insulation layer to expose a portion of the third conductive layer;
removing a portion of the third conductive layer to form a capacitor bottom plate;
removing the protective layer;
forming a capacitor dielectric adjacent the third conductive layer;
and
forming a fourth conductive layer adjacent the capacitor dielectric so as to form a top plate of the capacitor associated with each memory cell.

16 more elements

Dependencies are inferred from the claim text.

Method for fabricating stacked capacitor for a dynamic random access memory

Life of this patent

Method for fabricating stacked capacitor for a dynamic random access memory

Life of this patent

Abstract

Claims33