Method for reducing lateral silicide formation for salicide process by additional capping layer above gate
AssigneeUnited Microelectronics Corp.
InventorKing Yu Lu
Life of this patent
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Abstract
A method for reducing lateral silicide formation for a salicide process in a MOS manufacturing process is disclosed. In this method, a spacer structure is formed to be higher than a polysilicon layer of a gate structure, for example by providing a capping layer above the gate structure before the formation of the spacer structure. By this way, the distance between a silicide layer subsequently formed on the gate structure and that formed on the source/drain structure can be long enough to isolate the two silicide layers, thereby preventing the short circuit resulting from the lateral growth of silicide in the MOS structure.
Claims11
A method for reducing lateral silicide formation for a salicide process in an MOS manufacturing process, comprising steps of:
- a) providing a silicon substrate having thereon field oxide and gate oxide;
- b) overlying a polysilicon layer on the resulting silicon substrate;
- c) forming a capping layer on said polysilicon layer, said capping layer being formed of a material selected from a group consisting of silicon nitride (Si3N4), phosphosilicate glass (PSG) and titanium nitride (TiN);
- d) removing portions of said polysilicon layer and said capping layer to form a gate structure with a residual capping layer thereon;
- e) forming a spacer structure beside said gate structure and said residual capping layer;
- f) removing said residual capping layer after said spacer structure is formed so that said spacer structure has a level higher than a top surface of said polysilicon layer;
- and
- g) performing said salicide process.
Dependencies are inferred from the claim text.