Process for forming ultra-shallow source/drain extensions
AssigneeAdvanced Micro Devices, Inc.
InventorBin Yu
Life of this patent
Estimating the term…
Abstract
A method of fabricating an integrated circuit with ultra-shallow source and drain junctions utilizes a dummy or sacrificial gate spacer. Ions are implanted and dopants are provided through the openings associated with sacrificial spacers to form the source and drain extensions. The openings can be filled with an insulative layer. The process can be utilized for P-channel or N-channel metal oxide semiconductor field effect transistors (MOSFETS).
Claims20
A method of manufacturing an integrated circuit, comprising:
- providing a gate structure on a semiconductor substrate, the gate structure including a pair of sacrificial spacers, only one of the sacrificial spacers being on each side of the gate structure;
- providing a deep source region and a deep drain region, the gate structure being between the deep source region and the deep drain region, the deep source region and the deep drain region not including extensions;
- siliciding the deep source region, the deep drain region, and the gate structure;
- removing the sacrificial spacers from above a portion of the semiconductor substrate to leave a plurality of holes;
- forming an amorphous region through the holes within the portion of the semiconductor substrate and exclusive of the deep drain region and the deep source region, wherein the amorphous region is formed by ion implantation;
- and
- providing dopants to the amorphous region, thereby forming the extensions to the deep source region and the deep drain region.
A method of manufacturing an ultra-large scale integrated circuit including a plurality of field effect transistors having shallow source and drain extensions, the method comprising the steps of:
- providing at least part of a gate structure including a pair of dummy spacers on a top surface of a semiconductor substrate, the gate structure disposed between a deep source and a deep drain, the deep source and deep drain not including the shallow source and drain extensions, the gate structure including a single dummy spacer of the dummy spacers on each side of the gate structure;
- siliciding the deep source and the deep drain;
- removing the dummy spacers to form a first hole and a second hole;
- providing a silicon or germanium semiconductor implant through the first hole and through the second hole to amorphize the semiconductor substrate exclusive of the deep source and the deep drain;
- and
- then providing a dopant implant through the first hole and through the second hole to form the shallow source and drain extensions.
A process for forming shallow source extensions and shallow drain extensions on a substrate, the process comprising:
- forming a plurality of gate structures on a top surface of the substrate, each gate structure including a single pair of spacers;
- forming deep source drain regions on each side of the gate structures, the deep source drain regions not including the shallow source extensions and the shallow drain extensions;
- siliciding the deep source drain regions;
- removing the single pair of spacers from each gate structure, thereby exposing the top surface of the substrate;
- and
- implanting silicon or germanium through the exposed top surface of the substrate to form amorphous silicon regions exclusive of the deep source drain regions in the substrate;
- then providing a dopant through the exposed top surface of the substrate to create the shallow source extensions and the shallow drain extensions.
Dependencies are inferred from the claim text.