US 6,184,078 B2 · Method for fabricating a capacitor for a dynamic random access memory cell

Abstract

A method for fabricating a DRAM cell capacitor is applicable to a high density dynamic random access memory (DRAM) device on a semiconductor substrate wherein a storage node is formed on a buried contact pad in self-alignment. The method comprises forming a second insulator layer on the first insulator layer including the buried contact pad. An etching stopper layer is next formed on the second insulator layer. Sequentially, a third insulator layer and a first polysilicon layer are formed on the etching stopper layer. A masking layer is formed on the first polysilicon layer to define a storage node. The first polysilicon layer and the third insulator layer are sequentially etched using the masking layer until the etching stopper layer is exposed, so as to form a top via hole. A sidewall spacer is formed on both sidewalls of the top via hole. After removal of the masking layer, the etching stopper layer and the second insulator layer are sequentially etched using a combination of the first polysilicon layer and the sidewall spacer as a mask until the contact pad is exposed, so as to form a bottom via hole beneath the top via hole. A second polysilicon layer is deposited filling up the bottom and top via holes. The semiconductor substrate is planarized by CMP procedure until the third insulator layer is exposed. Finally, the third insulator layer is etched to form the cylindrical storage node having the sidewall spacer and the second polysilicon layer in self-alignment.

Claims16

Dependent claims

A method for fabricating a capacitor for a high density dynamic random access memory (DRAM) device on a semiconductor substrate having a buried contact pad formed thereon within a first insulator layer, comprising:

forming a second insulator layer on the first insulator layer, including on the buried contact pad;
forming a third insulator layer on the second insulator layer;
forming an etching stopper layer on the third insulator layer;
sequentially forming a fourth insulator layer and a first polysilicon layer on the etching stopper layer;
forming a masking layer on the first polysilicon layer to define a storage node;
sequentially etching the first polysilicon layer and the fourth insulator layer, using the masking layer as a first mask, until the etching stopper layer is exposed, to form a top via hole;
forming a sidewall spacer on an interior sidewall of the top via hole;
removing the masking layer;
etching the etching stopper layer and the second and third insulator layers, using a combination of the first polysilicon layer and the sidewall spacer as a second mask, until the buried contact pad is exposed, to form a bottom via hole beneath the top via hole;
depositing a second polysilicon layer to fill the bottom and top via holes;
planarizing the first polysilicon layer until the fourth insulator layer is exposed;
and
etching the fourth insulator layer to form the storage node of said capacitor.

10 more elements

Dependencies are inferred from the claim text.

Method for fabricating a capacitor for a dynamic random access memory cell

Life of this patent

Method for fabricating a capacitor for a dynamic random access memory cell

Life of this patent

Abstract

Claims16