Method of fabricating interconnect lines and plate electrodes of a storage capacitor in a semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorByeung-chul Kim
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Abstract
A method of fabricating a semiconductor device where the formation of a conductive layer typically over a storage capacitor on the device is used both as a plate electrode and also as an interconnect line. The method therefore combines the fabrication process steps of forming a plate electrode with the steps of forming a wiring layer. In a preferred embodiment, the storage capacitor is part of a cell array portion of a semiconductor memory device, whereas the interconnect line is in a peripheral portion of the memory device.
Claims9
A method of forming a portion of a semiconductor device, wherein the formed semiconductor device has at least one storage cell disposed in a cell array portion of a semiconductor memory device, and also has a peripheral circuit area disposed in a peripheral portion of the semiconductor memory device over a semiconductor substrate, the method comprising the steps of:
- forming a storage electrode in the cell array portion;
- forming a first conductive layer over the storage electrode, wherein the storage electrode and the first conductive layer comprise a storage cell capacitor for the semiconductor device, and the first conductive layer is patterned to form an interconnect line of the semiconductor device;
- forming an insulation layer overlying the first conductive layer;
- forming a contact hole extending from the top surface of the insulation layer, through the first conductive layer to the surface of the semiconductor substrate in the peripheral surface area in the semiconductor memory device;
- and
- forming a second conductive layer filling the contact hole so as to provide an electrical connection with the first conductive layer and the semiconductor substrate in the peripheral circuit area.
A method of forming a portion of a semiconductor device, wherein the formed semiconductor device has at least one storage cell, the method comprising:
- forming a storage electrode in the semiconductor device;
- forming a first conductive laver over the storage electrode, wherein the storage electrode and the first conductive layer comprise a storage cell capacitor for the semiconductor device, and the first conductive layer is patterned to form an interconnect line of the semiconductor device;
- forming first and second contact holes in the semiconductor memory device;
- forming a second conductive layer on the semiconductor memory device by depositing material in the first and second contact holes so as to provide a connection with the first conductive layer of the semiconductor device,
- wherein said step of forming a second conductive layer comprises the substep of depositing material in the first and second contact holes so as to provide a metal contact between the first and second contact holes,
- wherein said step of forming first and second contact holes comprises the substeps of
- forming the first contact hole over a first contact area on the first conductive layer;
- and
- forming the second contact hole over a second contact area on a substrate of the semiconductor device exclusive of the first conductive layer.
Dependencies are inferred from the claim text.