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US 6,184,046 B2Granted
Non-contact voltage stressing method for thin dielectrics at the wafer level
AssigneeTexas Instruments Incorporated
InventorJoe Patterson
Life of this patent
Estimating the term…
Abstract
A test apparatus and method that is used for a stress test of a semiconductor device.
Claims10
A device for measuring a defect, comprising:
- a semiconductor wafer;
- a grid positioned over said semiconductor wafer;
- said grid being bias with a voltage with respect to said semiconductor wafer;
- a light source for generating a light beam directed through the grid on said semiconductor wafer;
- a monitoring device responding to said light on said semiconductor wafer and said voltage to detect said defect.
2 more elements
A system for measuring a defect, comprising:
- a semiconductor wafer;
- a grid positioned over said semiconductor wafer;
- said grid being bias with a voltage with respect to said semiconductor wafer;
- a light source for generating a light beam directed through the grid on said semiconductor wafer;
- a monitoring device responding to said light on said semiconductor wafer and said voltage to detect said defect.
2 more elements
Dependencies are inferred from the claim text.