Semiconductor integrated circuit device
AssigneeFujitsu Limited
InventorsWaichirou Fujieda, Yasuharu Sato, Nobutaka Taniguchi, Hiroyoshi Tomita, Yasurou Matsuzaki
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Abstract
A semiconductor integrated circuit device includes a DLL circuit. The DLL circuit includes a frequency divider which frequency-divides an input clock at a frequency dividing ratio which is varied depending on a frequency of the input clock and thus results in a dummy clock and a reference clock. A delay system includes a variable delay circuit which delays the dummy clock. A control circuit controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.
Claims8
A semiconductor integrated circuit device comprising:
- a delayed locked loop circuit including:
- a frequency divider which frequency-divides an input clock at a frequency dividing ratio which is varied depending on a frequency of the input clock and thus results in a dummy clock and a reference clock;
- a delay system including a variable delay circuit which delays the dummy clock;
- and
- a control circuit which controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.
A semiconductor integrated circuit device comprising:
- a 1/2 frequency divider which frequency-divides an input clock at a frequency dividing ratio of 1/2;
- a selector circuit which selects one of the input clock and a frequency-divided clock from the 1/2 frequency divider in accordance with a frequency of the input clock;
- and
- a delayed locked loop circuit including:
- a frequency divider which frequency-divides a selected clock from the selector circuit and produces a dummy clock and a reference clock;
- a delay system including a variable delay circuit which delays the dummy clock;
- and
- a control circuit which controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.
Dependencies are inferred from the claim text.