US 6,175,525 B1Granted

Non-volatile storage latch

AssigneeHoneywell Inc.

InventorsDavid E. Fulkerson, Yong Lu, Allen T. Hurst, Jr., Jeffrey S. Sather, Jason B. Gadbois

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Abstract

A non-volatile latch having a power supply terminal and a ground terminal is disclosed. The non-volatile latch includes a pair of cross-coupled inverter elements each having a power supply terminal and a ground terminal. Magneto-resistive elements are interposed between the power supply terminals of both cross-coupled inverter elements and the power supply terminal of the non-volatile latch. In addition, magneto-resistive elements are interposed between the ground terminals of both cross-coupled inverter elements and the ground terminal of the non-volatile latch. By including magneto-resistive elements in each supply line, the effects of transistor parameter variation can be minimized.

Claims24

Dependent claims

A non-volatile latch having a first supply terminal and a second supply terminal, the non-volatile latch comprising:

a latching element having a first inverting logic element and a second inverting logic element coupled together in a cross-coupled configuration, wherein each of the first and second inverting logic elements has a power supply terminal and a ground terminal;
first magnetic means for providing a first magnetically programmable resistance value, the first magnetic means connected between the power supply terminal of the first inverting logic element and the first supply terminal of the latch;
second magnetic means for providing a second magnetically programmable resistance value, the second magnetic means connected between the ground terminal of the first inverting logic element and the second supply terminal of the latch;
third magnetic means for providing a third magnetically programmable resistance value, the third magnetic means connected between the power supply terminal of the second inverting logic element and the first supply terminal of the latch;
and
fourth magnetic means for providing a fourth magnetically programmable resistance value, the fourth magnetic means connected between the ground terminal of the second inverting logic element and the second supply terminal of the latch.

3 more elements

A non-volatile latch powered by a first voltage and a second voltage, comprising:

a first p-channel transistor having a gate terminal, a source terminal and a drain terminal;
a first n-channel transistor having a gate terminal, a source terminal and a drain terminal, the drain terminal of the first n-channel transistor is connected to the drain terminal of the first p-channel transistor, and the gate terminal of the first n-channel transistor is connected to the gate terminal of the first p-channel transistor;
a second p-channel transistor having a gate terminal, a source terminal and a drain terminal;
a second n-channel transistor having a gate terminal, a source terminal and a drain terminal, the drain terminal of the second n-channel transistor is connected to the drain terminal of the second p-channel transistor, and the gate terminal of the second n-channel transistor is connected to the gate terminal of the second p-channel transistor;
the drain terminal of the first n-channel transistor is connected to the gate terminal of the second n-channel transistor, and the drain terminal of the second n-channel transistor is connected to the gate terminal of the first n-channel transistor;
a first magnetic means for providing a first magnetically programmable resistance value connected between the source of the first p-channel transistor and the first voltage;
a second magnetic means for providing a second magnetically programmable resistance value connected between the source of the first n-channel transistor and the second voltage;
a third magnetic means for providing a third magnetically programmable resistance value connected between the source of the second p-channel transistor and the first voltage;
and
a fourth magnetic means for providing a fourth magnetically programmable resistance value connected between the source of the second n-channel transistor and the second voltage.

7 more elements

A non-volatile latch powered by a first voltage and a second voltage, comprising:

a first p-channel transistor having a gate terminal, a source terminal and a drain terminal;
a first n-channel transistor having a gate terminal, a source terminal and a drain terminal, the drain terminal of the first n-channel transistor is connected to the drain terminal of the first p-channel transistor, and the gate terminal of the first n-channel transistor is connected to the gate terminal of the first p-channel transistor;
a second p-channel transistor having a gate terminal, a source terminal and a drain terminal;
a second n-channel transistor having a gate terminal, a source terminal and a drain terminal, the drain terminal of the second n-channel transistor is connected to the drain terminal of the second p-channel transistor, and the gate terminal of the second n-channel transistor is connected to the gate terminal of the second p-channel transistor;
the drain terminal of the first n-channel transistor is connected to the gate terminal of the second n-channel transistor, and the drain terminal of the second n-channel transistor is connected to the gate terminal of the first n-channel transistor;
a third n-channel transistor having a source, a drain and a gate, the source of the third n-channel transistor is connected to the gate of the first n-channel transistor, the drain of the third n-channel transistor is connected to the gate of the second n-channel transistor, and the gate of the third n-channel transistor is coupled to an input terminal;
a first magnetic means for providing a first magnetically programmable resistance value connected between the source of the first p-channel transistor and the first voltage;
a second magnetic means for providing a second magnetically programmable resistance value connected between the source of the first n-channel transistor and the second voltage;
a third magnetic means for providing a third magnetically programmable resistance value connected between the source of the second p-channel transistor and the first voltage;
a fourth magnetic means for providing a fourth magnetically programmable resistance value connected between the source of the second n-channel transistor and the second voltage;
and
the magnetically programmable resistance value of each of the first magnetic means, the second magnetic means, the third magnetic means and the fourth magnetic means having two stable states, wherein the magnetically programmable resistance value of the first and fourth magnetic means is in one of the two stable states, and the magnetically programmable resistance value of the second and third magnetic means is in the other one of the two stable states.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/429,664Filed 28 Oct 1999 · continuation in part
Priority: 14 Apr 1998
Granted: 16 Jan 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 61/22
Comprising components having three or more electrodes, e.g. transistors: of the field-effect transistor [FET] type
G11C 7/20
Arrangements for writing information into, or reading information out from, a digital store: memory cell initialisation circuits, e.g. when…
G11C 11/161
Using elements in which the storage effect is based on magnetic spin effect: details concerning the memory cell structure, e.g. the layers of the…
G11C 11/1675
Auxiliary circuits: writing or programming circuits or methods