Phase locked loop clock source provided with a plurality of frequency adjustments
AssigneeSeiko Epson Corporation
InventorsMikio Shigemori, Hideo Karasawa, Toshihiko Kano, Kazushige Ichinose
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AssigneeSeiko Epson Corporation
InventorsMikio Shigemori, Hideo Karasawa, Toshihiko Kano, Kazushige Ichinose
Estimating the term…
An oscillator circuit having a first programmable divider for obtaining a reference signal by dividing the frequency of an oscillation signal of a piezoelectric resonator by a frequency dividing number M. A PLL circuit using the reference signal as input thereto to obtain a multiplied signal, the multiplied signal being formed by multiplying the input signal by a second frequency dividing number N for a second programmable divider provided in a feedback circuit. A third programmable divider capable of dividing the frequency of the multiplied signal by a third frequency dividing number X and outputting the frequency-divided signal. The frequency dividing numbers M, N, and X can be set to values independent of each other. Therefore, innumerable combinations of the frequency dividing numbers M, N, and X can be used and the number of frequencies producible by one oscillator can be largely increased by enabling selection of any suitable one of such combinations.
An oscillator comprising:
An oscillator comprising:
A frequency setting method for an oscillator comprising:
A frequency setting method for an oscillator comprising:
A frequency setting method for an oscillator comprising:
A frequency setting method for an oscillator comprising:
A frequency setting system for an oscillator, said frequency setting system outputting an oscillation signal of a first frequency by finely adjusting a resonant frequency of a piezoelectric resonator, outputting a reference signal of a second frequency by dividing the first frequency of the oscillation signal by a first frequency dividing number, operating a PLL circuit by using the reference signal as an input signal to the PLL circuit to form a multiplied signal of a third frequency, the multiplied signal being obtained by multiplying said input signal by a second frequency dividing number from a second programmable divider provided in a feedback circuit in the PLL circuit, said frequency setting system comprising:
Dependencies are inferred from the claim text.