US 6,151,254 A · Non-volatile semiconductor memory device and data erase method of non-volatile semiconductor memory device

Abstract

A non-volatile semiconductor memory device capable of reducing the erase voltage which is generated by a booster circuit and used for erasion of data stored therein is disclosed. The non-volatile semiconductor memory device comprises a memory cell array composed of a plurality of memory cells each having a control gate connected to a word line, a floating gate to which data is written and an erase gate for erasing the data of said floating gate on the basis of a first voltage applied thereto, a word decoder for selecting the word line, an erase gate decoder for selecting the erase gate and voltage applying means for generating the first voltage and applying the first voltage to the erase gates of the memory cells when the erase gate decoder outputs a second voltage lower than the first voltage to the erase gates of the memory cells. When the second voltage applied to the erase gate is held and a voltage based on the capacitance between the control gate and the erase gate is added to the second voltage when a predetermined voltage is applied from the word decoder through a word line to the erase gate and a resultant voltage is applied as the first voltage. Further, the capacitance between the erase gate and the floating gate is made sufficiently smaller than the capacitance between the erase gate and the control gate.

Claims9

Dependent claims

A non-volatile semiconductor memory device comprising:

a memory cell array comprising a plurality of memory cells each having a control gate connected to a word line, a floating gate to which a data is written and an erasing gate for erasing the data of said floating gate on a basis of an erasing potential thereto;
a potential applying circuit for applying a first potential to said erasing gate at a first state, rendering said erasing gate in a floating state at a second state, and applying a second potential to said control gate to change a potential of said erasing gate to said erasing potential that is higher than said first potential at a third state.

Dependencies are inferred from the claim text.

Non-volatile semiconductor memory device and data erase method of non-volatile semiconductor memory device

Life of this patent

Non-volatile semiconductor memory device and data erase method of non-volatile semiconductor memory device

Life of this patent

Abstract

Claims9