Memory cell integrated structure with corresponding biasing device

A biased memory cell, comprising:

• a cell transistor formed in a semiconductor substrate, the cell transistor including a substrate bias terminal;
• a bias transistor coupled between a first voltage reference and the substrate bias terminal and having a control terminal;
• a stabilization transistor coupled between the control terminal of the bias transistor and a second voltage reference and having a control terminal coupled to an enable signal;
• and
• a first regulation transistor coupled between the first voltage reference and the control terminal of the bias transistor, the first regulation transistor also having a control terminal coupled to the enable signal, the first regulation transistor being structured to be turned on by the enable signal while the stabilization transistor is turned off by the enable signal.

A method of biasing a substrate bias terminal of a memory cell integrated on a semiconductor substrate, the method comprising:

• connecting the substrate bias terminal with a positive bias via a relatively high current path during a read operation of the memory cell, the positive bias being sufficient to establish a relatively low threshold voltage in the memory cell during the read operation;
• interrupting the relatively high current path when the read operation has concluded;
• and
• keeping the substrate bias terminal connected to the positive bias via a relatively low current path both while the substrate bias terminal is connected by the relatively high current path and while the relatively high current path is interrupted.