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AssigneesSymetrix Corporation, Matsushita Electronics Corporation
InventorsShinichiro Hayashi, Tatsuo Otsuki, Carlos A. Paz de Araujo
Estimating the term…
A ferroelectric field effect transistor memory cell includes a thin film varistor located between the gate electrode and the ferroelectric layer. The varistor protects the ferroelectric layer from disturb voltage pulses arising from memory read, write and sense operations. A second electrode is located between the thin film varistor and the ferroelectric layer. The thin film ferroelectric is positioned over the channel of a transistor to operate as a ferroelectric gate. For voltages at which disturb voltages are likely to occur, the thin film varistor has a resistance obeying a formula R.sub.d >10.times.1/(2.pi.fC.sub.F), where R.sub.d is resistivity of the thin film varistor, f is an operating frequency of said memory, and C.sub.F is the capacitance of the ferroelectric layer. For voltages at or near the read and write voltage of the memory, the thin film varistor has a resistance obeying a formula R.sub.d <0.1.times.1/(2.pi.fC.sub.F).
An integrated circuit memory comprising:
A method of operating an integrated circuit memory comprising a thin film varistor and a thin film ferroelectric field effect transistor capable of switching between a first polarization state and a second polarization state, said method comprising the steps of:
Dependencies are inferred from the claim text.