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US 6,150,840 AGranted
Programmable reticle stitching
AssigneeAltera Corporation
InventorsRakesh Patel, John Turner
Life of this patent
Estimating the term…
Abstract
Design methodologies and techniques for significantly increasing logic density by stitching multiple reticles together are disclosed. The invention teaches various techniques to ensure continuity of interconnections and sealing mechanisms across the stitch region. The stitch extended device is readily scalable to allow quick transitions to next generation technologies.
Claims21
An electronic device comprising:
- a first semiconductor die, on a semiconductor wafer, comprising first logic circuitry coupled to a first plurality of interconnect lines, and further comprising a first buffer coupled to one of said first plurality of interconnect lines;
- a second semiconductor die, on said semiconductor wafer and adjacent to said first semiconductor die, comprising second logic circuitry coupled to a second plurality of interconnect lines, and further comprising a second buffer coupled to one of said second plurality of interconnect lines;
- and
- a stitch interconnect line extending over a stitch region on said semiconductor wafer between said first and said second semiconductor dies said, stitch interconnect line coupling said one of said first plurality of interconnect lines to one of said second plurality of interconnect lines,
- wherein, a geometric shape of said stitch interconnect line is modified compared with that of the interconnect lines on each die for preventing electrical discontinuity across reticle boundaries due to misalignment.
2 more elements
An electronic device comprising:
- a first semiconductor die comprising first logic circuitry coupled to a first plurality of interconnect lines;
- a second semiconductor die, comprising second logic circuitry coupled to a second plurality of interconnect lines;
- a stitch region between said first and said second semiconductor dies, wherein said first plurality of interconnect lines are coupled to said second plurality of interconnect lines;
- a first seal structure substantially surrounding edges of said first semiconductor die;
- and
- a second seal structure substantially surrounding edges of said second semiconductor die,
- wherein, said first seal structure and said second seal structure are configured at the edges of said stitch region to connect together to form a continuous ring around both said first and said second semiconductor dies.
4 more elements
An electronic device comprising:
- a first seal structure substantially surrounding edges of a first semiconductor die on a semiconductor wafer;
- and
- a second seal structure substantially surrounding edges of a second semiconductor die on said semiconductor wafer adjacent to said first semiconductor die,
- wherein, said first seal structure and said second seal structure are configured at the edges of a stitch region to connect together to form a continuous ring around both said first and said second semiconductor dies.
1 more element
A method of manufacturing an electronic device comprising the steps of:
- fabricating a first seal structure substantially surrounding edges of a first semiconductor die;
- fabricating a second seal structure substantially surrounding edges of a second semiconductor die, wherein the second semiconductor die is adjacent to the first semiconductor die;
- coupling said first seal structure on said first die to said second seal structure on said second die at the edges of a stitch region between said first and second die;
- and
- forming a continuous ring around both said first and said second semiconductor die.
2 more elements
Dependencies are inferred from the claim text.