Advanced nor-type mask ROM
AssigneeSamsung Electronics Co., Ltd.
InventorWoon-Kyung Lee
Life of this patent
Estimating the term…
Loading patent…
AssigneeSamsung Electronics Co., Ltd.
InventorWoon-Kyung Lee
Estimating the term…
A NOR-type mask ROM includes a semiconductor substrate of a first conductivity type. A plurality of buried diffusion regions of a second conductivity type opposite to the first conductivity type are arranged in parallel on the substrate to serve as sources and drains. A plurality of channel regions are defined between the buried diffusion regions and a plurality of gate insulating layers are formed on the channel regions. A plurality of gate regions are formed in parallel on the gate insulating layers, intersecting the buried diffusion regions, and overlapping with the channel regions, to be provided as word lines. An insulating layer is deposited on the overall surface of the substrate, covering the gate regions, and a plurality of sub-gate regions are formed into spacers on the sidewalls of the insulating layer, in parallel with the gate regions, for increasing a cell current.
A NOR-type mask ROM comprising:
A NOR-type mask ROM having a cell array region, an interface region, and a peripheral region, the NOR-type mask ROM comprising:
Dependencies are inferred from the claim text.