Short channel non-self aligned VMOS field effect transistor

A field effect transistor (FET) comprising:

• a semiconductor substrate having a surface with a (100) plane, said substrate having a trench opening for a gate therein and having a width at the substrate surface and V-shaped angled walls extending from the surface of and converging together in the interior of said substrate, said V-shaped walls at the bottom of the trench curve toward each other to create a round and concave shape only at bottom of the trench;
• an insulating layer disposed on the walls of the opening for said gate for insulating the gate from said substrate;
• a gate material disposed in said opening on said insulating layer and having a gate width at the substrate surface wider than the width of the trench opening to define a gate region;
• source and drain regions disposed in said substrate and on opposite sides of said gate with the edge of each of their metallurgical junctions abutting the underside of the insulating layer on one of said angled walls;
• an impurity underlying the channel and being opposite in type to the impurity of the source and drain to create a double diffused (DMOS) FET, said opposite impurity type extending from slightly below the source and drain metallurgical junctions and to a point above the bottom of the gate trench and varying in concentration along the channel with the lightest concentration being at the deepest point of the impurity in the substrate;
• and
• conductive contacts electrically connected to each of the source, drain and gate and each contact being insulated from the other, whereby, when a voltage is applied to said drain contact, a depletion region forms from the bottom of the trench and extends to the field insulation on the drain side of the DMOS to create an effective channel length only between the metallurgical edge of said source adjacent the gate and the bottom of the trench and is of a length of less than about one-half of the gate width.