Combination test structures for in-situ measurements during fabrication of semiconductor devices
AssigneeTexas Instruments Incorporated
InventorsMahalingam Nandakumar, Greg C. Baldwin, Andrew T. Appel
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Abstract
A first test structure (40) is used to measure both the gate resistance/linewidth and transistor performance. A gate line (42) crosses a moat region (44) with source (48) and drain (50) regions formed on either side of the gate line (42). The gate line (42) is connected to four probe pads (52) in an H configuration for accurate linewidth measurements. A second test structure (70) may be used alone or in conjunction with the first test structure. A single gate line (72) crosses a moat region (74) several times. This allows both capacitance and gate gate-resistance measurements with the same test structure and for more accurate TLD measurement.
Claims10
A test structure comprising:
- a first moat region located in a semiconductor body;
- an isolation region surrounding said moat region;
- a gate line crossing over said moat region, said gate line connected to at least four probe pads;
- a source region and a drain region formed in said moat region on opposite sides of said gate line.
A test structure comprising:
- a moat region located in a semiconductor body;
- a serpentine gate line crossing over said moat region, said serpentine gate line connected to a probe pad at each end;
- source/drain regions located in said moat regions adjacent said serpentine gate line.
Dependencies are inferred from the claim text.