Method for fabricating a high bias device

A method for fabricating a high-bias semiconductor device, the method comprising:

• providing a semiconductor substrate doped with a first-type dopant, wherein a well doped with a second-type dopant is formed on the substrate, wherein if the first-type dopant is an N-type dopant then the second-type dopant is a P-type dopant, and if the first-type dopant is a P-type dopant then the second-type dopant is an N-type dopant;
• performing at least two ion implantation processes with the first-type dopant and a different dopant energy to respectively form at least two drift region layers, wherein the at least two drift region layers follow a condition that a lower drift region layer has a lighter dopant density and a greater thickness;
• forming a first pad oxide layer over the drift region layers;
• forming a first silicon nitride layer on the first pad oxide layer;
• forming a trench, which goes through the silicon nitride layer, the first pad oxide layer, and the drift region layers to expose the well;
• removing the first pad oxide layer and the first silicon nitride layer;
• forming a second pad oxide layer over the substrate;
• forming a second silicon nitride layer over the substrate other than each sidewall of the trench;
• forming a field oxide layer on each sidewall of the trench;
• removing the second silicon nitride layer and the second pad oxide layer;
• forming a gate oxide layer over a trench bottom region;
• forming a trench gate, which fills a void of the trench and overflows onto the gate oxide layer;
• and forming a source region in a top one of the drift region layers on one side of the trench gate, and a drain region in the top one of the drift region layers on the other side of the trench gate.