Memory cell that includes a vertical transistor and a trench capacitor

A process for forming an array of memory cells each comprising a pass transistor and a storage capacitor for a dynamic random access memory in a portion of a silicon body in which there have been formed p-type and n-type conductivity wells and in which active areas for individual cells have been defined and isolated comprising the steps of:

• forming at the top surface of the silicon body a source/drain for the pass transistor of each memory cell;
• forming vertically in each active area a trench of a first depth that passes through a surface well of a first conductivity type and a buried well of the opposite conductivity type;
• forming in each trench a first dielectric layer useful as the dielectric layer of a storage capacitor on a sidewall along a portion of the trench in the buried well;
• providing in each trench a first polycrystalline silicon layer opposite the first dielectric layer for forming a storage capacitor with the adjacent portion of the silicon body;
• providing in each trench a second doped polycrystalline silicon layer that lies above the first polycrystalline silicon layer and that makes electrical contact with the first polycrystalline layer in the trench;
• diffusing dopants from the second polycrystalline layer into an adjacent portion of the silicon body for forming in the silicon body an output terminal for each pass transistor;
• forming in each trench a dielectric layer on the sidewall portion of the trench of the pass transistor and an oxide layer on top of the second polysilicon layer of the pass transistor and over the second polycrystalline layer;
• and
• forming in each trench a third polycrystalline silicon layer electrically isolated from the second polycrystalline silicon layer and adjacent to the gate dielectric for serving as the gate and gate contact of the pass transistor.