US 6,150,199 AGranted

Method for fabrication of programmable interconnect structure

AssigneeQuickLogic Corporation

InventorsRalph G. Whitten, Richard L. Bechtel, Mammen Thomas, Hua-Thye Chua, Andrew K. Chan, John M. Birkner

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Abstract

In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

Claims2

Dependent claims

A method for fabricating a field of programmable gate array, comprising the steps of:

forming logic circuits for performing logic functions;
forming I/O circuits for performing I/O functions;
forming a first level of conductive routing channels, said first level channels being connected to select input and output terminals of said logic and I/O circuits;
forming an insulating layer overlaying said first level routing channels;
forming openings through said insulating layer at selected locations and terminating said openings upon selected channels of said first level routing channels;
blanket depositing using plasma enhanced chemical vapor deposition a film of amorphous silicon upon said insulating layer, wherein said film is within said openings and contacts said first level channels at said select locations;
patterning said amorphous silicon film to form at said selected locations respective amorphous silicon film areas;
forming a second level of conductive routing channels, said second level channels being connected to select input and output terminals of said logic and I/O circuits, and being transverse to said first level channels and in contact with and overlaying said amorphous silicon film areas at said selected locations;
and
wherein the process parameters of said plasma enhanced chemical vapor deposition includes a temperature and gaseous environment selected to yield a leakage current at said selected locations of less than about 10 nanoamperes at 5.5 voltage.

7 more elements

Dependencies are inferred from the claim text.