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AssigneeMicron Technology, Inc.
InventorMonte Manning
Estimating the term…
A semiconductor processing method of making electrical connection between an electrically conductive line and a node location includes, a) forming an electrically conductive line over a substrate, the substrate having an outwardly exposed silicon containing node location to which electrical connection is to be made, the line having an outer portion and an inner portion, the inner portion laterally extending outward from the outer portion and having an outwardly exposed portion, the inner portion having a terminus adjacent the node location, and b) electrically connecting the extending inner portion with the node location. An integrated circuit is also described. The integrated circuit includes a semiconductor substrate, a node location on the substrate, and a conductive line over the substrate which is in electrical communication with the node location. The conductive line includes an outer portion and an inner portion. The outer portion has a terminus and the inner portion extends laterally away from the outer portion terminus and generally toward the node location. The inner portion is in electrical communication with the node location.
An integrated circuit of claim 1 wherein the node location comprises a diffusion region within the semiconductor substrate.
An integrated circuit comprises:
An integrated circuit comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Of conductive parts of the interconnections: local interconnections
Generic packages, interconnections, connectors or other constructional details of devices covered by
Term ended 20 Aug 2016 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
This invention relates to an integrated circuit and semiconductor processing methods of making electrical connection between an electrically conductive line and a node location.
Single semiconductor devices are grouped into integrated circuits, which in turn are further densified into large scale integrated semiconductor systems. The trend in semiconductor integrated circuitry fabrication continues to involve a decrease in the size of individual structures. However, this has been accompanied by an increase in the complexity and number of such structures aggregated on a single semiconductor integrated chip.
One type of integrated circuitry comprises memory circuitry. This invention arose out of problems or challenges inherent in producing a particular type of memory circuitry, namely static random access memory (SRAMs). Such circuitry typically interconnects a gate of one transistor device to a diffusion area of another transistor device in a semiconductor substrate. One typical prior art method of accomplishing such fabrication and interconnection is described with reference to FIGS. 1-4.
Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
FIG. 1 is a diagrammatic sectional view of a prior art semiconductor wafer fragment at one prior art processing step, and is discussed in the "Background" section above.
FIG. 2 is a view of the FIG. 1 prior art wafer fragment at a prior art processing step subsequent to that shown by FIG. 1.
This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws "to promote the progress of science and useful arts" (Article 1, Section 8).
In accordance with one aspect of the invention, a semiconductor processing method of making electrical connection between an electrically conductive line and a node location comprises the steps of:
providing a substrate having an outer dielectric surface and a node location to which electrical connection is to be made;