Backside exposure of desired nodes in a multi-layer integrated circuit
AssigneeAdvanced Micro Devices, Inc.
InventorsXia Li, Daniel Yim
Life of this patent
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Abstract
Aspects for exposing local areas for desired nodes in a multi-layer integrated circuit from the backside are described. In an exemplary method aspect, the method includes removing a predetermined portion of a first backside layer, opening chosen local areas with focused ion beam etching through at least the first backside layer, and exposing a desired node in a metal layer lower than the first backside layer with reactive ion etching. The method further includes removing the predetermined portion by performing reactive ion etching to a predetermined stop point. Alternatively, the first backside layer is mechanically polished to a predetermined thickness. Additionally, the method includes utilizing a high current ion beam during the focused ion beam etching.
Claims6
A multi-layer integrated circuit structure with limited frontside access and having one or more exposed nodes, the structure comprising:
- a first backside layer;
- at least one lower level metal layer;
- and
- at least one interdielectric layer between the first backside layer and the at least one lower level metal layer, wherein exposure of a desired node of the at least one lower level metal layer results from reducing the first backside layer to a predetermined thickness, exposing at least one local area window through at least the first backside layer for at least one desired node, and etching to the at least one desired node through the at least one local area window by global delayering.
A multi-layer integrated circuit structure with limited frontside access and having one or more exposed nodes, the structure comprising:
- a first backside layer;
- at least one lower level metal layer;
- and
- at least one interdielectric layer between the first backside layer and the at least one lower level metal layer, wherein exposure of a desired node of the at least one lower level metal layer results from reducing the first backside layer to a predetermined thickness, exposing at least one local area window through at least the first backside layer for at least one desired node, and etching to the at least one desired node through the at least one local area window by global delayering including reactive ion etching through the at least one dielectric layer.
Dependencies are inferred from the claim text.