US 6,147,385 A · CMOS static random access memory devices

Abstract

A full CMOS SRAM cell having the capability of having a reduced aspect ratio is described. The SRAM cell includes first and second transfer transistors of n-channel types, first and second driving transistors of the n-channel types and first and second load transistors of p-channel types. Each of the transistors has source and drain regions on opposite sides of a channel region formed in a semiconductor substrate and a gate over the channel region. The cell includes a first common region defined by the drain regions of the first transfer transistor and the first driving transistor connected in series therethrough. A second common region is defined by the drain regions of the second transfer transistor and the second driving transistor connected in series therethrough. The drain region of the first load transistor is disposed adjacent to the first common region between the first and second common regions. The drain region of the second load transistor is disposed between the drain region of the first load transistor and the second common region. First and second gate electrode layers are disposed generally parallel to each other, and respectively serving as the gates of the first driving transistor and the first load transistor and as the gates of the second driving transistor and the second load transistor, wherein each of the first and second gate electrode layers is made of a conductive material of a first level. First and second interconnecting layers are each made of a conductive material of a second level different from the first level, the first interconnecting layer connecting the first common region to the drain region of the first load transistor and the second gate electrode layer, the second interconnecting layer connecting the second common region to the drain region of the second load transistor and the first gate electrode layer.

Claims23

Dependent claims

A static random access memory cell including first and second transfer transistors of n-channel type, first and second driving transistors of the n-channel type and first and second load transistors of p-channel type, each of said transistors having source and drain regions on opposite sides of a channel region formed in a semiconductor substrate and a gate over the channel region, said cell comprising:

a first common region defined by the drain regions of said first transfer transistor and said first driving transistor connected in series therethrough;
a second common region defined by the drain regions of said second transfer transistor and said second driving transistor connected in series therethrough;
the drain region of said first load transistor disposed adjacent said first common region between said first and second common regions;
the drain region of said second load transistor disposed between the drain region of said first load transistor and said second common region;
first and second gate electrode layers disposed generally parallel to each other, said first gate electrode layer serving as the gates of said first driving transistor and said first load transistor and said second gate electrode layer serving as the gates of said second driving transistor and said second load transistor, each of said first and second gate electrode layers being made of a conductive material at a first level of said memory;
and
first and second interconnecting layers each made of a conductive material at a second level of said memory cell different from said first level, said first interconnecting layer connecting said first common region to the drain region of said first load transistor and to said second gate electrode layer, said second interconnecting layer connecting said second common region to the drain region of said second load transistor and to said first gate electrode layer.

4 more elements

A semiconductor memory device including at least one memory cell disposed in a cell region defined on a semiconductor substrate, said cell including first and second transfer transistors, first and second driving transistors and first and second load transistors each of which has a pair of source/drain regions on opposite sides of a channel region in said substrate and a gate over the channel region, one of the source/drain regions of said first transfer transistor being connected in series with one of the source/drain regions of said first driving transistor for providing a first common region, one of the source/drain regions of said second transfer transistor being connected in series with one of the source/drain regions of said second driving transistor for providing a second common region, said first common region being connected to one of the source/drain regions of said first load transistor and to the gates of said second load transistor and said second driving transistor, said second common region being connected to one of the source/drain regions of said second load transistor and to the gates of said first load transistor and said first driving transistor, the other of the source/drain regions of each of said first and second transfer transistors being connected to a corresponding one of a pair of data lines, the improvement of said device comprising:

a first active region formed in said substrate in said cell region and extending in a first direction to provide the others of the source/drain regions of said first transfer transistor and said first driving transistor, the channel regions thereof and said first common region;
and
a second active region formed spaced apart from said first active region in said substrate in said cell region and extending in said first direction to provide the others of the source/drain regions of said second transfer transistor and said second driving transistor, the channel regions thereof and said second common region.

A semiconductor device including memory cells respectively formed in cell regions on a semiconductor substrate, said cell regions defined by row and column lines bounding respective ones of said cell regions, said row lines divided into alternate first and second row lines, said column lines divided into alternate first and second column lines, each of said cells including a flip-flop with cross-coupled first and second inverters, and first and second transfer transistors connected to said flip-flop, said first and second inverters respectively having first and second diffusion regions in said substrate to be connected to a ground source, said device comprising:

first bridge regions formed in said substrate such that each of said first bridge regions is interconnected through a corresponding one of intersections of said first row lines and said first column lines with said first diffusion region in each of four cell regions contiguous to said corresponding one of the intersections thereof;
and
second bridge regions formed in said substrate such that each of said second bridge regions is interconnected through a corresponding one of intersections of said second row lines and said second column lines with said second diffusion region in each of four cell regions contiguous to said corresponding one of the intersections thereof;
whereby said second bridge regions crossing each of said second row lines are arranged in a staggered relationship with respect to said first bridge regions crossing each of two first row lines adjacent to said each of said second row lines.

1 more element

Dependencies are inferred from the claim text.

CMOS static random access memory devices

Life of this patent

CMOS static random access memory devices

Life of this patent

Abstract

Claims23