Method for forming a DRAM cell with a stacked capacitor
AssigneeNational Semiconductor Corporation
InventorsAlexander Kalnitsky, Albert Bergemont
Life of this patent
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Abstract
A dynamic random-access-memory (DRAM) cell with a fin or wing-type stacked capacitor is fabricated by using a layer of polysilicon as an etch stop rather than the layer of nitride that is conventionally used. By using the layer of polysilicon, the problem of hydrogen-enhanced boron diffusion in dual work function CMOS transistors is eliminated while at the same time increasing the capacitance of the stacked capacitor without substantially increasing the step height of the capacitor.
Claims16
A method for forming a dynamic random-access-memory (DRAM) cell with a stacked capacitor in a substrate of a first conductivity type, the cell including:
- an access transistor having:
- spaced-apart source and drain regions of a second conductivity type formed in the substrate,
- a channel region defined in the substrate between the source and drain regions,
- a layer of gate oxide formed above the channel region, and
- a gate formed on the layer of gate oxide from a first layer of polysilicon (poly-1);
- and
- a layer of insulation material formed to contact the gate and the source and drain regions, the layer of insulation material being free of a layer of silicon nitride;
- the method comprising the steps of:
- forming a second layer of polysilicon (poly-2) on the layer of insulation material to contact the layer of insulation material;
- forming a first layer of sacrificial material on the layer of poly-2;
- forming a third layer of polysilicon (poly-3) on the first layer of sacrificial material;
- forming a second layer of sacrificial material on the layer of poly-3;
- selectively etching the second layer of sacrificial material, the layer of poly-3, the first layer of sacrificial material, the layer of poly-2, and the layer of insulation material to form a contact opening that exposes a contact area on the surface of the drain region, the contact opening having sidewalls;
- and
- forming a fourth layer of polysilicon (poly-4) on the second layer of sacrificial material, the sidewalls of the contact opening, and the contact area.
A method for forming a dynamic random-access-memory (DRAM) cell with a stacked capacitor in a substrate of a first conductivity type, the cell including:
- an access transistor having:
- spaced-apart source and drain regions of a second conductivity type formed in the substrate,
- a channel region defined in the substrate between the source and drain regions,
- a layer of gate oxide formed above the channel region, and
- a gate formed on the layer of gate oxide from a first layer of polysilicon (poly-1);
- and
- a layer of insulation material formed to contact the gate and the source and drain regions, the layer of insulation material being free of a layer of silicon nitride;
- the method comprising the steps of:
- forming a second layer of polysilicon (poly-2) on the layer of insulation material to contact the layer of insulation material;
- forming a layer of sacrificial material on the layer of poly-2;
- selectively etching the second layer of sacrificial material, the layer of poly-2, and the layer of insulation material to form a contact opening that exposes a contact area on the surface of the drain region, the contact opening having sidewalls;
- and
- forming a third layer of polysilicon (poly-3) on the layer of sacrificial material, the sidewalls of the contact opening, and the contact area.
Dependencies are inferred from the claim text.