US 6,146,950 A · Method of manufacturing multiple metallic layered embedded ROM

Abstract

A method of manufacturing multiple metallic layered embedded ROM. A substrate has a memory cell region and a peripheral circuit region. A first gate and a first source/drain region are formed in the memory cell region. A second gate and a second source/drain region are formed in the peripheral circuit region. A first dielectric layer is formed over the substrate. A first contact is formed in the first dielectric layer in the periphery circuit region. A first patterned metallic layer that couple electrically with the first contact is formed in the peripheral circuit region. A second dielectric layer is formed over the substrate. A portion of the second dielectric layer in the memory cell region is removed to form a remaining second dielectric layer having a sloping sidewall surrounds a periphery of the memory cell region. A via hole is formed in the second dielectric layer in the peripheral circuit region and a second contact opening is formed in the first dielectric layer in the memory cell region. The via hole exposes the first patterned metallic layer. A metallic barrier layer is formed over the substrate. Ions are implanted into coded regions in the substrate. A second patterned metallic layer is formed in the peripheral circuit region to cover the second dielectric layer and fill the via hole. A third patterned metallic layer is formed in the memory cell region to fill the contact opening. A passivation layer is formed over the substrate.

Claims16

Dependent claims

A method of manufacturing multiple metallic layered embedded read-only-memory (ROM), comprising:

providing a substrate having a memory cell region and a peripheral circuit region thereon;
forming a first gate and a first source/drain region in the memory cell region;
forming a second gate and a second source/drain region in the peripheral circuit region;
forming a first dielectric layer over the substrate;
forming a first contact in the first dielectric layer in the periphery circuit region;
forming a first patterned metallic layer that couple electrically with the first contact in the peripheral circuit region;
forming a second dielectric layer over the substrate;
removing a portion of the second dielectric layer in the memory cell region to form a remaining second dielectric layer having a sloping sidewall surrounds a periphery of the memory cell region;
forming a via hole in the second dielectric layer in the peripheral circuit region and a second contact opening in the first dielectric layer in the memory cell region, wherein the via hole exposes the first patterned metallic layer;
forming a metallic barrier layer over the substrate;
coding by implanting ions into coded regions in the substrate;
forming a second patterned metallic layer in the peripheral circuit region to cover the second dielectric layer and fill the via hole to electrically coupled with the first patterned metallic layer;
forming a third patterned metallic layer in the memory cell region to fill the contact opening;
and
forming a passivation layer over the substrate.

12 more elements

A method of manufacturing multiple metallic layered embedded read-only-memory (ROM), comprising the steps of:

providing a substrate having a memory cell region and a peripheral circuit region thereon;
forming a first gate and a first source/drain region in the memory cell region;
forming a second gate and a second source/drain region in the peripheral circuit region;
forming a first dielectric layer over the substrate;
forming a first metallic interconnect layer in the peripheral circuit region, wherein the first metallic interconnect layer includes a conductive line and a plug;
forming a second dielectric layer over the substrate;
removing a portion of the second dielectric layer in the memory cell region to leave a remaining second dielectric layer having a sloping sidewall surrounds a periphery of the memory cell region;
forming a via hole in the second dielectric in the peripheral circuit region and a contact opening in the first dielectric layer in the memory cell region, wherein the via hole exposes the first metallic interconnect layer;
coding by implanting ions into coded regions in the substrate;
forming a second metallic interconnect layer on the second dielectric layer to fill the dielectric layer opening in the peripheral circuit region;
forming a first patterned metallic layer in the memory cell region to fill the contact opening;
and
forming a passivation layer over the substrate.

10 more elements

Dependencies are inferred from the claim text.

Method of manufacturing multiple metallic layered embedded ROM

Life of this patent

Method of manufacturing multiple metallic layered embedded ROM

Life of this patent

Abstract

Claims16