Large angle implantation to prevent field turn-on under select gate transistor field oxide region for non-volatile memory devices

A method of fabricating a non-volatile memory, comprising the steps of:

• (a) providing a substrate;
• (b) providing a field oxide on the substrate, the field oxide comprising a core field oxide region having a field oxide surface, a select drain gate transistor field oxide region and a select source gate transistor field oxide region;
• (c) providing a polysilicon layer on the field oxide, the polysilicon layer comprising a select drain gate strip and a select source gate strip disposed opposite each other, the core field oxide region positioned between the select drain gate strip and the select source gate strip, the select drain gate strip positioned on the select drain gate transistor field oxide region, and the select source gate strip positioned on the select source gate transistor field oxide region;
• and
• (d) implanting a P-type dopant into the substrate below the select drain gate transistor field oxide region at a tilt angle of at least 8.degree. with respect to the field oxide surface.

A method of fabricating a NAND device on a substrate of a semiconductor wafer, the NAND device having a characteristic of a high field threshold voltage for preventing field turn-on, the method comprising the steps of:

• (a) providing a field oxide on the substrate, the field oxide comprising a select drain gate transistor field oxide region and a core field oxide region having a field oxide surface;
• (b) forming a select drain gate strip on the select drain gate transistor field oxide region;
• and
• (c) implanting a P-type dopant into the substrate below the select drain gate transistor field oxide region through the field oxide surface at a tilt angle of at least 8.degree. with respect to the field oxide surface.

A method of fabricating a non-volatile memory, comprising the steps of:

• (a) providing a substrate on a semiconductor wafer;
• (b) providing a field oxide on the substrate, the field oxide including a core field oxide region having a field oxide surface, a select drain gate transistor field oxide region and a select source gate transistor field oxide region;
• (c) providing a polysilicon layer on the field oxide;
• (d) etching the polysilicon layer to form a select drain gate strip and a select source gate strip disposed opposite each other, the core field oxide region positioned between the select drain gate strip and the select source gate strip, the select drain gate strip positioned on the select drain gate transistor field oxide region, and the select source gate strip positioned on the select source gate transistor field oxide region;
• (e) implanting a P-type dopant selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), indium (In) and thallium (Tl) into the substrate below the select drain gate transistor field oxide region through the field oxide surface and the select drain gate transistor field oxide region at a tilt angle of at least 8.degree. with respect to the field oxide surface;
• (f) rotating the semiconductor wafer by about 180.degree.;
• and
• (g) implanting the P-type dopant into the substrate below the select source gate transistor field oxide region through the field oxide surface and the select source gate transistor field oxide region at a tilt angle of at least 80 with respect to the field oxide surface.