US 6,146,939 AGranted

Metal-polycrystalline silicon-N-well multiple layered capacitor

AssigneeTritech Microelectronics, Ltd.

InventorUday Dasgupta

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Abstract

A stacked capacitor that has a large capacitance per unit area (Co), very low voltage coefficient (Kv), and an acceptable parasitic capacitance factor (Kp) is described that uses only one polysilicon layer. The stacked capacitor is formed at the surface of a semiconductor substrate of a first conductivity type. The stacked capacitor has a bottom plate that is formed by a lightly doped well diffused into the surface of the semiconductor substrate. The bottom plate also has a first plurality of interconnected conductive layers of a first conductive material disposed above and aligned with the well, whereby a first conductive layer of the first plurality of conductive layers is connected to the well by multiple contacts distributed over an area of the well. The stacked capacitor further has a top plate with a second conductive layer of a second conductive material such as a highly doped polycrystalline silicon placed between the well and the first conductive layer and has openings distributed over a surface area of the conductive material to allow the multiple contacts to connect the well and the first conductive layer. The top plate further has second plurality of interconnected conductive layers of the first conductive material connected to the second conductive layer and interleaved between each layer of the first plurality of conductive layers. Additionally the stacked capacitor has a dielectric having a plurality of insulating layers to electrically isolate each of the conductive layers from each other.

A method for fabricating a stacked capacitor at the surface of a semiconductor substrate, comprising the steps of:

diffusing a material of a first conductivity type to a lightly doped concentration into the surface of the semiconductor substrate to form a diffusion well;
diffusing the material of the first conductivity type to a highly doped concentration into the surface of the semiconductor substrate within the well to form a plurality of contacts distributed within said well, whereby the plurality of contacts decrease the resistivity of the well to prevent depletion of charges present in said well;
forming a first insulating layer on the surface of said semiconductor substrate;
forming a first conductive layer of a first conductive material upon said first insulating layer aligned with said diffusion well;
forming contact openings in the first insulating layer and the first conductive layer aligned with and above the plurality of contacts;
forming a second insulating layer on the first conductive layer;
reforming the contact openings in the second insulating laver aligned with the plurality of contacts and isolated from the first conductive layer to re-expose said plurality of contacts;
placing a contact material within said openings to connect to the plurality of contacts;
forming a second conductive layer of a second conductive material on the second insulating layer in connection with the contact material;
forming a first plurality of conductive layers of the second conductive material aligned with and connected through at least one first interlayer via to the first conductive layer;
forming a second plurality of conductive layers of the second conductive material aligned with and connected through at least one second interlayer via to the second conductive layer, whereby each layer of the second plurality is interleaved between two layers of the first plurality of conductive layers;
and
forming a plurality of insulating layers between each layer of the first and second plurality of conductive layers.

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Abstract

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