US 6,146,933 A · Field shield isolated transistor

Abstract

A field shield isolated transistor is provided wherein the left-hand edge (E1) of a left-hand contact pad (51a) is positioned a distance (d5) to the right of the left-hand edge (F1) of a left-hand field shield gate electrode (41); the right-hand edge (E2) of the left-hand contact pad (51a) is positioned a distance (d6) to the right of the right-hand edge (F2) of the left-hand field shield gate electrode (41); the left-hand edge (E3) of a right-hand contact pad (52a) is positioned a distance (d7) to the left of the left-hand edge (F3) of a right-hand field shield gate electrode (42); and the right-hand edge (E4) of the right-hand contact pad (52a) is positioned a distance (d8) to the left of the right-hand edge (F4) of the right-hand field shield gate electrode (42). The right-hand edge (E2) of the left-hand contact pad (51a) and the left-hand edge (E3) of the right-hand contact pad (52a) which are positioned closer to diffusion layers (21-23) reduce the size of the MOS transistor, achieving the effective use of the area thereof.

Claims1

Dependent claims

A method of manufacturing an isolated transistor comprising the steps of:

(a) forming first and second diffusion layers in a semiconductor substrate extending in first and second directions orthogonal to each other, to arrange said first and second diffusion layers in said first direction, and forming a gate oxide film on said semiconductor substrate between said first diffusion layer and said second diffusion layer;
(b) forming a gate electrode including a coupling portion on said gate oxide film and first and second contact pads with a first patterned mask to constitute a MOS transistor with said first and second diffusion layers;
(c) forming first and second insulator with a second patterned mask to dispose said first insulator on a first side of said first and second diffusion layers in said second direction and to dispose said second insulator on a second side of said first and second diffusion layers in said second direction, said second side being opposite from said first side,
wherein a margin is smaller than a deviation for an alignment of said first and second masks.

1 more element

Dependencies are inferred from the claim text.

Field shield isolated transistor

Life of this patent

Field shield isolated transistor

Life of this patent

Abstract

Claims1