Programmable fractional frequency digital frequency synthesizer for synchronous residual time stamp service clock regenerator phase locked loop

A method of generating a clock signal with a nominal frequency of Fc/(N+K/L) Hz over each successive interval of L periods, where N, K and L are integers, and L>K, and wherein Fc is a system clock, comprising the steps of:

• (a) organizing each set of L periods, including a first set of K periods and a second set of L-K periods, by interleaving two or more non-null subsequences of periods of the first set with two or more non-null subsequences of periods of the second set,
• (b) during each period of one of the subsequences of the first set, outputting the clock with a frequency of Fc/(N+1) Hz,
• (c) during each period of one of the subsequences of the second set, outputting the clock with a frequency of Fc/N Hz,
• counting from 0 to L-1 and generating an M bit binary representation of the count,
• comparing each m.sup.th bit of the count L with an (M-m-1).sup.th bit K(M-m-1) of an M bit binary representation of K(0:M-1), where 0.ltoreq.m.ltoreq.M-1
• if any compared pair of bits L(m) and K(M-m-1) are both 1 and each lesser significant bit L(m-1), L(m-2), . . . , L(1), L(0) is 0, performing step (b), and
• otherwise, performing step (c).

A digital frequency synthesizer for generating a clock signal with a nominal frequency of Fc/(N+K/L) Hz over each successive interval of L periods, where N, K and L are integers, and L>K, and wherein Fc is a system clock, comprising:

• comparator circuitry for organizing each set of L periods, including a first set of K periods and a second set of L-K periods, by interleaving two or more non-null subsequences of periods of the first set with two or more non-null subsequences of periods of the second set,
• a frequency divider receiving a signal with period Fc and an indication from the comparator circuitry for outputting as the clock, a fir signal having a frequency of Fc/(N+1) Hz, during each period of one of the subsequences of the first set, and outputting as the clock, a second signal having the frequency of Fc/N Hz, during each period of one of the subsequences of the second set,
• a counter for counting the periods of the clock such that periods of the first signal with the frequency Fc/(N+1) Hz are counted only during periods of the subsequences of the first set and periods of the second signal with the frequency of Fc/N Hz are counted only during periods of the subsequences of the second set,
• the comparator circuitry receiving the count of the counter and generating the indication for switching between outputting the first signal as the clock and outputting the second signal as the clock based on the count obtained from the counter.

A digital frequency synthesizer for generating a clock signal with a nominal frequency of Fc/(N+K/L) Hz over each successive interval of L periods, where N, K and L are integers, and L>K, and wherein Fc is a system clock, comprising:

• comparator circuitry for organizing each set of L periods, including a first set of K periods and a second set of L-K periods, by interleaving two or more non-null subsequences of periods of the first set with two or more non-null subsequences of periods of the second set, and
• a frequency divider receiving a clock signal with period Fc and an indication from the comparator circuitry for outputting a clock signal having a frequency of Fc/(N+1) Hz, during each period of one of the subsequences of the first set, and outputting a clock signal having the frequency of Fc/N Hz, during each period of one of the subsequences of the second set, and
• a counter for counting from 0 to L-1 and generating an M bit binary representation of the count L(0:M-1),
• said comparator circuitry further comprising M multiplexers, each m.sup.th multiplexer comparing each m.sup.th bit of the count L(m) with an (M-m-1).sup.th bit K(M-m-1) of an M bit binary representation of K(0:M-1), where 0.ltoreq.m.ltoreq.M-1, said M multiplexers having their inputs and outputs connected in tandem so that if any compared pair of bits L(m) and K(M-m-1) are both 1 and each lesser significant bit L(m-1), L(m-2), . . . , L(1), L(0) is 0, said comparator circuitry outputs an indication for outputting said clock signal with a frequency of Fc/(N+1) and otherwise outputs an indication for outputting said clock signal with a frequency of Fc/N.