ESD bus lines in CMOS IC's for whole-chip ESD protection

An apparatus of preventing integrated circuits from interfering by electrostatic-discharge (ESD), wherein said apparatus comprises:

• a plurality of first internal circuits, each of said plurality of first internal circuits having an first input pad and an first output pad, input signals being input to said plurality of first internal circuits through said first input pad and output signals being output from said plurality of first internal circuits through said first output pad, each of said plurality of first internal circuits being coupled with a first power line and a second power line;
• a plurality of second internal circuits, each of said plurality of second internal circuits having an second input pad and an second output pad, input signals being input into said plurality of second internal circuits from said second input pad and output signals being output from said plurality of second internal circuits through said second output pad, each of said plurality of second internal circuits being coupled with a third power line and a fourth power line;
• a plurality of first ESD bi-directional connection devices;
• a plurality of second ESD bi-directional connection devices;
• a plurality of third ESD bi-directional connection devices, each of said third ESD bi-directional connection devices coupled with one of said plurality of second internal circuits through said third power line;
• a plurality of fourth ESD bi-directional connection devices, each of said fourth ESD bi-directional connection devices coupled with one of said plurality of second internal circuits through said fourth power line;
• a first ESD bus coupled with said plurality of first ESD bi-directional connection devices;
• a second ESD bus coupled with said plurality of second ESD bi-directional connection devices and said plurality of third ESD bi-directional connection devices;
• a third ESD bus coupled with said plurality of fourth ESD bi-directional connection devices;
• and
• a plurality of ESD clamp device, wherein said first ESD bus, said second ESD bus and said third ESD bus being coupled together through said plurality of ESD clamp device for discharging a current caused by said plurality of internal circuits through said plurality of first ESD bi-directional connection device to said first ESD bus, through said plurality of second ESD bi-directional connection devices and said plurality of third ESD bi-directional connection devices to said second ESD bus.

A method for electrostatic discharging of an integrated circuit, comprises:

• conducting an electrostatic-discharge (ESD) current from an internal circuit of said integrated circuit into a power line of said internal circuit;
• conducting said ESD current into an ESD bi-directional connection device;
• conducting said ESD current into a first ESD bus of said integrated circuit;
• conducting said ESD current into an ESD clamp device to discharge said ESD current;
• and
• conducting said ESD current into an second ESD bus of said integrated circuit to unify voltage level of said first ESD bus and said second ESD bus.