US 6,144,241 AGranted

Versatile gate-array cell with interstitial transistors for compact flip-flops with set or clear

AssigneePericom Semiconductor Corp.

InventorAnthony Yap Wong

Life of this patent

Estimating the term…

Loading patent…

Abstract

A gate-array cell uses smaller and larger transistors. Four larger transistors are provided: two n-channel and two p-channel. A small p-channel transistor is placed between the contact tabs of the polysilicon lines of the two larger p-channel transistors, and between the p-channel transistors and a N-well tap. A small n-channel transistor is similarly placed between the contact tabs of polysilicon lines of the two larger n-channel transistors, and between the n-channel transistors and a P-well tap. The cell is slightly expanded in height to accommodate the two smaller transistors. The smaller transistors enable a reduction in the number of transistors required for latches and flip-flops. The smaller transistors allow a feedback inverter to directly connect to an input, since the input can easily over-power the feedback current. This is not possible for standard gate array cells having only one transistor size. Transmission gates are eliminated when direct feedback is feasible. Thus, the smaller transistors enable a reduction in transistor count as well as being smaller in size. Clear and set are provided by larger pull-down or pull-up transistors rather than NAND gates, since the larger pull-down and pull-up transistors can easily over-power the feedback inverters.

Claims20

Dependent claims

A gate-array cell having large and small transistors, the gate-array cell comprising:

a large p-channel active area having a first large p-channel transistor and a second large p-channel transistor, the first large p-channel transistor formed where a first polysilicon line crosses the large p-channel active area, the second large p-channel transistor formed where a second polysilicon line crosses the large p-channel active area;
a small p-channel active area having a small p-channel transistor;
an N-well tap for providing a substrate bias to bulk terminals of the first and second large p-channel transistors and the small p-channel transistor;
a large n-channel active area having a first large n-channel transistor and a second large n-channel transistor, the first large n-channel transistor formed where a third polysilicon line crosses the large n-channel active area, the second large n-channel transistor formed where a fourth polysilicon line crosses the large n-channel active area;
a small n-channel active area having a small n-channel transistor;
a P-well tap for providing a substrate bias to bulk terminals of the first and second large n-channel transistors and the small n-channel transistor;
wherein the small p-channel transistor has a maximum current drive of less than one-quarter of a maximum current drive of the first large p-channel transistor, and wherein a maximum current drive of the first large p-channel transistor is substantially equivalent to maximum current drive of the second large p-channel transistor;
and
wherein the small n-channel transistor has a maximum current drive of less than one-quarter of a maximum current drive of the first large n-channel transistor, and wherein a maximum current drive of the first large n-channel transistor is substantially equivalent to maximum current drive of the second large n-channel transistor,
whereby the gate-array cell contains four large and two small transistors.

7 more elements

A gate-array cell layout comprising:

a large p-channel active area having a first large p-channel transistor and a second large p-channel transistor, the first large p-channel transistor formed where a first polysilicon line crosses the large p-channel active area, the second large p-channel transistor formed where a second polysilicon line crosses the large p-channel active area;
a small p-channel active area having a small p-channel transistor;
a large n-channel active area having a first large n-channel transistor and a second large n-channel transistor, the first large n-channel transistor formed where a third polysilicon line crosses the large n-channel active area, the second large n-channel transistor formed where a fourth polysilicon line crosses the large n-channel active area;
a small n-channel active area having a small n-channel transistor;
wherein the small p-channel transistor has a maximum current drive of less than one-quarter of a maximum current drive of the first large p-channel transistor, and wherein a maximum current drive of the first large p-channel transistor is substantially equivalent to maximum current drive of the second large p-channel transistor;
and
wherein the small n-channel transistor has a maximum current drive of less than one-quarter of a maximum current drive of the first large n-channel transistor, and wherein a maximum current drive of the first large n-channel transistor is substantially equivalent to maximum current drive of the second large n-channel transistor,
whereby the gate-array cell contains four large and two small transistors.

5 more elements

Dependencies are inferred from the claim text.