CMOS inverter using gate induced drain leakage current
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorMin-hwa Chi
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Abstract
An inverter formed in a semiconductor substrate is disclosed. The inverter comprises: a p-well formed in the substrate, the p-well being the output of the inverter; a gate structure formed atop the p-well, the gate structure being the input of the inverter and being formed from a thin gate oxide layer underneath a conductive layer; an n- base formed adjacent to a first edge of the gate structure; a p+ structure formed within the n- base; and a n+ structure adjacent a second edge of the gate structure.
Claims14
An inverter formed in a semiconductor substrate comprising
- a p-well formed in said substrate, said p-well being the output of said inverter;
- a gate structure formed atop said p-well, said gate structure being the input of said inverter and being formed from a thin gate oxide layer underneath a conductive layer;
- an n- base formed adjacent to a first edge of said gate structure;
- a p+ structure formed within said n- base;
- and
- a n+ structure adjacent a second edge of said gate structure.
An inverter formed in a semiconductor substrate comprising
- an n-well formed in said substrate, said n-well being the output of said inverter;
- a gate structure formed atop said n-well, said gate structure being the input of said inverter and being formed from a thin gate oxide layer underneath a conductive layer;
- an p- base formed adjacent to a first edge of said gate structure;
- a n+ structure formed within said p- base;
- and
- a p+ structure adjacent a second edge of said gate structure.
Dependencies are inferred from the claim text.