Monolithically-integrated static random access memory device
AssigneeLucent Technologies Inc.
InventorsGerhard Hobler, Marco Mastrapasqua, Mark Richard Pinto, Enrico Sangiori
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Abstract
A monolithically-integrated SRAM cell is described for reducing the cell size, i.e., at least two of a plurality of transistors comprising the SRAM cell are monolithically integrated to define a first transistor and a second transistor, wherein the drain of the first transistor functions as the gate of the second transistor and the drain of the second transistor functions as the gate of the first transistor. This integration eliminates the need for gate-to-drain connections of previous devices.
Claims16
A SRAM cell comprising a plurality of transistors wherein
- at least two of the transistors are monolithically integrated in a structure comprising a first semiconducting layer, a second semiconducting layer, and an insulating layer therebetween,
- the first and second semiconducting layers each comprising a source, drain, channel and gate to define first and second transistors,
- the insulating layer is disposed between the channel of the first transistor and the channel of the second transistor;
- and
- the gate of the first transistor functions as the drain of the second transistor and the gate of the second transistor functions as the drain of the first transistor.
A SRAM cell comprising a plurality of transistors, in which at least two of the plurality of transistors defining a first transistor and a second transistor each comprise a gate, source, drain, and a channel and are monolithically integrated with an insulating layer is disposed between the channel of the first transistor and the channel of the second transistor, wherein the drain of the first transistor functions as the gate of the second transistor and the drain of the second transistor functions as the gate of the first transistor and the insulating layer separates the channel of the first transistor from the channel of the second transistor to define an integrated transistor structure,
- wherein the integrated transistor structure is fabricated by
- (a) growing a layer of bulk silicon to form the first transistor, growing the insulating layer over the bulk silicon layer with selective epitaxial lateral overgrowth, and growing a layer of epitaxial silicon over the insulating layer to form the second transistor, and
- (b) implanting antimony and arsenic dopants in the layers defined by step (a) along first and second channeling directions, respectively, to form the gate and drain of the first and second transistors, the first channeling direction being displaced by an angle of about 45 degrees from a vertical axial line running through the integrated transistor structure and along a latitudinal plane thereof, and the second channeling direction being displaced by an angle of about 45 degrees from the vertical axial line and along a longitudinal plane thereof.
A SRAM cell comprising a plurality of transistors including a first and a second transistor comprising:
- a first semiconducting layer having dopants implanted therein to define a first source and a first drain for the first transistor
- a second semiconducting layer having dopants implanted therein to define a second source and a second drain for the second transistor, wherein the first drain of the first transistor functions as the gate of the second transistor and the second drain of the second transistor functions as the gate of the first transistor, and
- an insulating layer disposed between the first and second semiconducting layers, wherein the insulating layer separates the channel of the first transistor from the channel of the second transistor, and the first and second semiconducting layers and insulating layer define a monolithically-integrated structure.
Dependencies are inferred from the claim text.