Method for forming alignment mark
AssigneeOki Electric Industry Co., Ltd.
InventorsYasuhiro Yamamoto, Akira Watanabe
Life of this patent
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Abstract
A method for forming an alignment mark includes defining a circuit pattern area and an alignment mark area on a semiconductor substrate, forming a first pattern in the alignment mark area, forming a second pattern of a first material on the first pattern, forming a layer of a second material different from the first on the entire surface of the semiconductor substrate, and polishing the layer of the second material and the second layer such that the second pattern and the layer of second material are polished at different speed, until a step difference appears between the second pattern and the layer.
Claims22
A method for forming an alignment mark, comprising:
- defining a circuit pattern area and an alignment mark area on a semiconductor substrate;
- forming a first pattern within the alignment mark area;
- forming a second pattern of first material on the first pattern;
- forming a layer of second material different from the first material on an entire surface of the semiconductor substrate;
- and
- polishing the layer of the second material and the second pattern such that the second pattern and the layer of second material are polished at different speed, until a step difference appears between the second pattern and the layer of second material.
A method for forming an alignment mark, comprising:
- defining a circuit pattern area and an alignment mark area on a semiconductor substrate;
- forming a first pattern within the alignment mark area;
- forming a first layer of a first material on an entire surface of the semiconductor substrate;
- forming a second pattern on the first pattern in the alignment mark area by etching the first layer, and forming a contact hole in the first layer by etching the first layer;
- forming a second layer of a second material different from the first material on an entire surface of the semiconductor device, and
- polishing the second layer and the second pattern by a CMP process such that the first and the second material are polished at different speed, until a step difference appears between the second layer and the second pattern.
A method for forming an alignment mark, comprising:
- defining a circuit pattern area and an alignment mark area on a semiconductor substrate;
- forming a first pattern within the alignment mark area;
- forming a first layer of a first material on an entire surface of the semiconductor substrate;
- forming a second pattern on the first pattern in the alignment mark area by etching the first layer, and forming a wiring pattern by etching the first layer;
- forming a second layer of a second material different from the first material an entire surface of the semiconductor substrate, and
- polishing the second layer and the second pattern by a CMP process such that the first and the second material are polished at different speed, until a step difference appears between the second layer and the second pattern.
Dependencies are inferred from the claim text.